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| features ? high performance, low power atmel ? avr ? 8-bit microcontroller ? advanced risc architecture ? 130 powerful instructions ? mo st single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 16mips throughput at 16mhz (atmega165pa/645p) ? up to 20mips throughput at 20mhz (atmega165a/325a/325pa/645a/3250a/3250pa/6450a/6450p) ? on-chip 2-cycle multiplier ? high endurance non-volatile memory segments ? in-system self-programmable flash program memory ? 16kbytes (atmega165a/atmega165pa) ? 32kbytes (atmega325a/atmega325pa/atmega3250a/atmega3250pa) ? 64kbytes (atmega645a/atmega645p/atmega6450a/atmega6450p) ?eeprom ? 512bytes (atmega165a/atmega165pa) ? 1kbytes (atmega325a/atmega325pa/atmega3250a/atmega3250pa) ? 2kbytes (atmega645a/atmega645p/atmega6450a/atmega6450p) ?internal sram ? 1kbytes (atmega165a/atmega165pa) ? 2kbytes (atmega325a/atmega325pa/atmega3250a/atmega3250pa) ? 4kbytes (atmega645a/atmega645p/atmega6450a/atmega6450p) ? write/erase cycles: 10,000 flash/100,000 eeprom ? data retention: 20 years at 85c/100 years at 25 c (1) ? optional boot code section with independent lock bits ? in-system programming by on-chip boot program ? true read-while-write operation ? programming lock for software security ? qtouch ? library support ? capacitive touch buttons, sliders and wheels ? qtouch and qmatrix acquisition ? up to 64 sense channels ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities according to the jtag standard ? extensive on-chip debug support ? programming of flash, eeprom, fuses, and lock bits through the jtag interface ? peripheral features ? two 8-bit timer/counters with se parate prescaler and compare mode ? one 16-bit timer/counter with separate prescaler, compare mode, and capture mode ? real time counter with separate oscillator ? four pwm channels ? 8-channel, 10-bit adc ? programmable serial usart ? master/slave spi serial interface ? universal serial interface with start condition detector ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? interrupt and wake-up on pin change ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated oscillator ? external and internal interrupt sources ? five sleep modes: idle, adc noise reduct ion, power-save, power-down, and standby ? i/o and packages ? 54/69 programmable i/o lines ? 64/100-lead tqfp, 64-pad qfn/mlf and 64-pad drqfn ? speed grade: ? atmega 165a/165pa/645a/645p: 0 - 16mhz @ 1.8 - 5.5v ? atmega325a/325pa/3250a/3250pa/6450a /6450p: 0 - 20mhz @ 1.8 - 5.5v ? temperature range: ?-40c to 85 c industrial ? ultra-low power consumption (picopower devices) ? active mode: ? 1mhz, 1.8v: 215a ? 32khz, 1.8v: 8a (including oscillator) ? power-down mode: 0.1a at 1.8v ? power-save mode: 0.6a at 1.8v (including 32khz rtc note: 1. reliability qualification results show that the projected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c. 8-bit atmel microcontroller with 16/32/64k bytes in-system programmable flash atmega165a atmega165pa atmega325a atmega325pa atmega3250a atmega3250pa atmega645a atmega645p atmega6450a atmega6450p preliminary rev 8285b?avr?03/11
2 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 1. pin configurations 1.1 pinout - tqfp and qfn/mlf figure 1-1. 64a (tqfp)and 64m1 (qfn/mlf) pinout atmega165a/atmega165pa/atmega325a/atmega325pa/atmega645a/atmega645p note: the large center pad underneath the qfn/mlf packages is made of metal and internally connected to gnd. it should be sol- dered or glued to the board to ensure good mechanical stability. if the center pad is left unconnected, the package might loose n from the board. 64 63 62 47 46 48 45 44 43 42 41 40 39 38 37 36 35 33 34 2 3 1 4 5 6 7 8 9 10 11 12 13 14 16 15 17 61 60 18 59 20 58 19 21 57 22 56 23 55 24 54 25 53 26 52 27 51 29 28 50 49 32 31 30 pc0 vcc gnd pf0 (adc0) pf7 (adc7/tdi) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck) pf5 (adc5/tms) pf6 (adc6/tdo) aref gnd avcc (rxd/pcint0) pe0 (txd/pcint1) pe1 dnc (xck/ain0/pcint2) pe2 (ain1/pcint3) pe3 (usck/scl/pcint4) pe4 (di/sda/pcint5) pe5 (do/pcint6) pe6 (clko/pcint7) pe7 (ss/pcint8) pb0 (sck/pcint9) pb1 (mosi/pcint10) pb2 (miso/pcint11) pb3 (oc0a/pcint12) pb4 (oc2a/pcint15) pb7 (t1) pg3 (oc1b/pcint14) pb6 (t0) pg4 (oc1a/pcint13) pb5 pc1 pg0 pd7 pc2 pc3 pc4 pc5 pc6 pc7 pa7 pg2 pa6 pa5 pa4 pa3 pa0 pa1 pa2 pg1 pd6 pd5 pd4 pd3 pd2 (int0) pd1 (icp1) pd0 (tosc1) xtal1 (tosc2) xtal2 reset/pg5 gnd vcc index corner 3 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 1.2 pinout - 100a (tqfp) figure 1-2. pinout atmega3250a/atmega3250pa/atmega6450a/atmega6450p (oc2a/pcint15) pb7 dnc (t1) pg3 (t0) pg4 reset/pg5 vcc gnd (tosc2) xtal2 (tosc1) xtal1 dnc dnc (pcint26) pj2 (pcint27) pj3 (pcint28) pj4 (pcint29) pj5 (pcint30) pj6 dnc (icp1) pd0 (int0) pd1 pd2 pd3 pd4 pd5 pd6 pd7 avcc agnd aref pf0 (adc0) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck) pf5 (adc5/tms) pf6 (adc6/tdo) pf7 (adc7/tdi) dnc dnc ph7 (pcint23) ph6 (pcint22) ph5 (pcint21) ph4 (pcint20) dnc dnc gnd vcc dnc pa0 pa1 pa2 pa3 pa4 pa 5 pa6 pa7 pg2 pc7 pc6 dnc ph3 (pcint19) ph2 (pcint18) ph1 (pcint17) ph0 (pcint16) dnc dnc dnc dnc pc5 pc4 pc3 pc2 pc1 pc0 pg1 pg0 index corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 dnc (rxd/pcint0) pe0 (txd/pcint1) pe1 (xck/ain0/pcint2) pe2 (ain1/pcint3) pe3 (usck/scl/pcint4) pe4 (di/sda/pcint5) pe5 (do/pcint6) pe6 (clko/pcint7) pe7 vcc gnd dnc (pcint24) pj0 (pcint25) pj1 dnc dnc dnc dnc (ss/pcint8) pb0 (sck/pcint9) pb1 (mosi/pcint10) pb2 (miso/pcint11) pb3 (oc0a/pcint12) pb4 (oc1a/pcint13) pb5 (oc1b/pcint14) pb6 tqfp 4 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 2. overview the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p is a low-power cmos 8-bit microcon- troller based on the avr enhanced risc architecture. by exec uting powerful instructions in a single clock cycle, this microcontroller achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power con- sumption versus processing speed. 2.1 block diagram figure 2-1. block diagram the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. program cou n ter i n ter n al oscillator watchdog timer stack poi n ter program flash mcu co n trol register sram ge n eral purpose registers i n structio n register timer/ cou n ters i n structio n decoder data dir. reg. portb data dir. reg. porte data dir. reg. porta data dir. reg. portd data register portb data register porte data register porta data register portd timi n g a n d co n trol oscillator i n terrupt u n it eeprom spi usart status register z y x alu portb dri v ers porte dri v ers porta dri v ers portf dri v ers portd dri v ers portc dri v ers pb0 - pb7 pe0 - pe7 pa0 - pa7 pf0 - pf7 v cc g n d xtal1 xtal2 co n trol li n es + - a n alog comparator pc0 - pc7 8 -bit data bus reset calib. osc data dir. reg. portc data register portc o n -chip debug jtag tap programmi n g logic bou n dary- sca n data dir. reg. portf data register portf adc pd0 - pd7 data dir. reg. portg data reg. portg portg dri v ers pg0 - pg4 ag n d aref a v cc u n i v ersal serial i n terface a v r cpu porth dri v ers ph0 - ph7 data dir. reg. porth data register porth portj dri v ers pj0 - pj6 data dir. reg. portj data register portj 5 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 the atmega165a/165pa/325a/325pa/3250a/3250pa/ 645a/645p/6450a/6450p provides the following features: 16k/32k/64k bytes of in-system programmable flash with read- w hile- w rite capabilities, 512/1k/2k bytes eeprom, 1k/2k/4k byte sram, 54/ 69 general purp ose i/o lines, 32 general purpose working registers, a jtag interface for boundary-scan, on-chip debugging support and programming, three flexible timer/counters with compare modes, internal and external interrupts, a serial programmable usart, universal serial interface with start condi- tion detector, an 8-channel, 10-bit adc, a programmable w atchdog timer with internal oscillator, an spi serial port, and five software selectable power saving modes. the idle mode stops the cpu while allo wing the sram, timer/counters, spi port, and interrupt system to con- tinue functioning. the power-do wn mode saves the register cont ents but freeze s the oscillator, disabling all other chip functions until the next interrupt or hardware reset. in power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o mod- ules except asynchronous timer and adc, to mi nimize switching noise during adc conversions. in standby mode, the crys tal/resonator oscillator is running while the rest of the device is sleep- ing. this allows very fast start-up combined with low-power consumption. atmel offers the qtouch ? library for embedding capacitive t ouch buttons, sliders and wheels functionality into avr microcontrollers. the patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes adjacent key suppression ? (akstm ? ) technology for unambiguous detection of key events. the easy-to-use qtouch suite toolchain allows you to explore, develop and debug your own touch applications. the device is manufactured using atmel?s high density non-volatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot pro- gram running on the avr core. the boot program can use any interface to download the application program in the applic ation flash memory. software in the boot flash section will continue to run while the application fl ash section is updated, providing true read- w hile- w rite operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel devise is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p avr is sup- ported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in -circuit emulators, and evaluation kits. 6 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 2.2 comparison between atmega165a/165pa/325a/325pa/3250a/ 3250pa/645a/645 p/6450a/6450p 2.3 pin descriptions 2.3.1 vcc digital supply voltage. 2.3.2 gnd ground. 2.3.3 port a (pa7:pa0) port a is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port a pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p as listed on ?alter- nate functions of port b? on page 76 . 2.3.4 port b (pb7:pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b has better driving capabilities than the other ports. port b also serves the functions of various special features of the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p as listed on ?alter- nate functions of port b? on page 76 . table 2-1. differences between: atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p device flash eeprom ram mhz atmega165a 16kbyte 512bytes 1kbyte 16 atmega165pa 16kbyte 512bytes 1kbyte 16 atmega325a 32kbyte 1kbyte 2kbyte 20 atmega325pa 32kbyte 1kbyte 2kbyte 20 atmega3250a 32kbytes 1kbyte 2kbyte 20 atmega3250pa 32kbyte 1kbyte 2 byte 20 atmega645a 64kbyte 2kbyte 4kbyte 16 atmega645p 64kbyte 2kbyte 4kbyte 16 atmega6450a 64kbyte 2kbyte 4kbyte 20 atmega6450p 64kbyte 2kbyte 4kbyte 20 7 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 2.3.5 port c (pc7:pc0) port c is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port c output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port c pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port c also serves the functions of special features of the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p as listed on ?alter- nate functions of port d? on page 79 . 2.3.6 port d (pd7:pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port d pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special features of the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p as listed on ?alter- nate functions of port d? on page 79 . 2.3.7 port e (pe7:pe0) port e is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port e output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port e pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. port e also serves the functions of various special features of the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p as listed on ?alter- nate functions of port e? on page 80 . 2.3.8 port f (pf7:pf0) port f serves as the analog inputs to the a/d converter. port f also serves as an 8-bit bi-directional i/o port, if the a/d converter is not used. port pins can provide internal pull-up resistors (selected for each bit). the port f output buffers have sym- metrical drive characteristics with both high sink and source capa bility. as inputs, port f pins that are externally pulled low will source current if the pull-up resistors are ac tivated. the port f pins are tri-stated when a reset condition becomes active, even if the clock is not running. if the jtag interface is enabled, the pull-up resistors on pins pf7( tdi), pf5(tms), and pf4(tck) will be activated even if a reset occurs. port f also serves the functions of the jtag interface, see ?alternate functions of port f? on page 82 . 2.3.9 port g (pg5:pg0) port g is a 6-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port g output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port g pins that are extern ally pulled low will sour ce current if the pull-up resistors are activated. the port g pins are tri-stated when a reset condition becomes active, even if the clock is not running. 8 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 port g also serves the functions of various special features of the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p as listed on page 84 . 2.3.10 port h (ph7:ph0) port h is a 8-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port h output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port h pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port h pins are tri-stated when a reset condition becomes active, even if the clock is not running. port h also serves the functions of various special features of the atmega3250a/3250pa/6450a/6450p as listed on page 85 . 2.3.11 port j (pj6:pj0) port j is a 7-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port j output buffers have symmetrical drive characteristics with both high sink and source capa- bility. as inputs, port j pins that are externally pulled low will source current if the pull-up resistors are activated. the port j pins are tr i-stated when a reset condition becomes active, even if the clock is not running. port j also serves the functions of various special features of the atmega3250a/3250pa/6450a/6450p as listed on page 87 . 2.3.12 reset reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 27-13 on page 326 . shorter pulses are not guaranteed to generate a reset. 2.3.13 xtal1 input to the inverting oscillato r amplifier and input to the in ternal clock operating circuit. 2.3.14 xtal2 output from the invert ing oscillator amplifier. 2.3.15 avcc avcc is the supply voltage pin for port f and the a/d converter. it should be externally con- nected to v cc , even if the adc is not used. if the adc is used, it should be connected to v cc through a low-pass filter. 2.3.16 aref this is the analog reference pin for the a/d converter. 9 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 3. resources a comprehensive set of development tools, app lication notes and datasheets are available for download on http:// www.atmel.com/avr. 4. data retention reliability qualification results show that the pr ojected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c. 5. about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. these code examples assume that the part specific header file is included before compilation. for i/o registers located in extended i/o map, "i n", "out", "sbis", "sbic", "cbi", and "sbi" instructions must be replaced with instructio ns that allow access to extended i/o. typically "lds" and "sts" combined with "sbrs", "sbrc", "sbr", and "cbr". 10 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 6. avr cpu core 6.1 introduction this section discusses the avr core architecture in general. the main function of the cpu core is to ensure correct program execution. the cpu must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 6.2 architectural overview figure 6-1. block diagram of the avr architecture in order to maximize performance and parallelism, the avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are executed with a sing le level pipelining. w hile one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is in-system reprogrammable flash memory. the fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. this allows single-cycle ar ithmetic logic unit (alu ) operation. in a typ- flash program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control i/o lines eeprom data bus 8-bit data sram direct addressing indirect addressing interrupt unit spi unit w atchdog timer analog comparator i/o module 2 i/o module1 i/o module n 11 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 ical alu operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-b it indirect address register pointers for data space addressing ? enabling efficient address calculations. one of the these address pointers can also be used as an address pointer for look up tables in flash program memory. these added function registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operations between registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic opera- tion, the status register is updated to reflect information about the result of the operation. program flow is provided by conditional and uncon ditional jump and call instructions, able to directly address the whole address space. most avr instructions have a single 16-bit word for- mat. every program memory address contains a 16- or 32-bit instruction. program flash memory space is divided in two sections, the boot program section and the application program section. both sections have dedicated lock bits for write and read/write protection. the spm instruction that writes into the application flash memory section must reside in the boot program section. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and consequently the stack size is only limited by the to tal sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read/write accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control r egisters in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector posi- tion. the lower the interrupt vector address, the higher the priority. the i/o memory space contains 64 addresses for cpu peripheral functi ons as control regis- ters, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5f. in addition, the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p has extended i/o space from 0x60 - 0xff in sram where only the st/sts/std and ld/lds/ldd instructions can be used. 6.3 alu ? arithm etic logic unit the high-performance avr alu operates in dire ct connection with all the 32 general purpose working registers. w ithin a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. the alu operations are divided into three main categories ? arithmetic, logical, and bit-functions. some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. see the ?instruction set? section for a detailed description. 6.4 avr status register the status register contains information about the result of the most recently executed arithme- tic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the status register is updated after all alu operations, as specified in the instruction set reference. this will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. 12 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. this must be handled by software. 6.4.1 sreg ? avr status register the sreg is defined as: ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set for th e interrupts to be enabled. the individual inter- rupt enable control is then performed in separate control registers. if the global interrupt enable register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. the i-bit can also be set and cleared by the application with the sei and cli instructions, as described in the instruction set reference. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (b it store) use the t-bit as source or desti- nation for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in so me arithmetic operations. half carry is useful in bcd arithmetic. see the ?instruction set description? for detailed information. ? bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two?s complement overflow flag v. see the ?instruction set description? for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v suppor ts two?s complement arithmetics. see the ?instruction set description? for detailed information. ? bit 2 ? n: negative flag the negative flag n indicates a negative result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the ?instruction set description? for de tailed information. bit 76543210 0x3f (0x5f) i t h s v n z c sreg read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 13 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 6.5 general purpose register file the register file is optimized for the avr enhanc ed risc instruction set. in order to achieve the required performance and flex ibility, the following in put/output schemes ar e supported by the register file: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input figure 6-2 shows the structure of the 32 general purpose working registers in the cpu. figure 6-2. avr cpu general purpose w orking registers most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. as shown in figure 6-2 , each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. although not being physically imple- mented as sram locations, this memory organization provides great flexibility in access of the registers, as the x-, y- and z-pointer registers can be set to index any register in the file. 6.5.1 the x-register, y-register, and z-register the registers r26...r31 have some added functions to their general purpose usage. these reg- isters are 16-bit address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as described in figure 6-3 on page 14 . 7 0 addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f w orking r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte 14 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 6-3. the x-, y-, and z-registers in the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 6.6 stack pointer the stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. note that the stack is implemented as growing from higher to lower memory locations. the stack pointer register always points to the top of the stack. the stack pointer points to the data sram stack area where the subroutine and interrupt stacks are loca ted. a stack push command will decrease the stack pointer. the stack in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. initial stack pointer value equals the last address of the internal sram and the stack pointer must be set to point above start of the sram, see figure 7-2 on page 20 . see table 6-1 for stack pointer details. the avr stack pointer is implemented as two 8- bit registers in the i/o space. the number of bits actually used is implementation dependent. note that the data space in some implementa- tions of the avr architecture is so small that only spl is needed. in this case, the sph register will not be present. 15 xh xl 0 x-register 707 0 r27 (0x1b) r26 (0x1a) 15 yh yl 0 y-register 707 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 7070 r31 (0x1f) r30 (0x1e) table 6-1. stack pointer instructions instruction stack pointer description push decremented by 1 data is pushed onto the stack call icall rcall decremented by 2 return address is pushed onto the stack with a subroutine call or interrupt pop incremented by 1 data is popped from the stack ret reti incremented by 2 return address is po pped from the stack with return from subroutine or return from interrupt 15 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 6.6.1 sph and spl ? stack pointer 6.7 instruction execution timing this section describes the general access timi ng concepts for instruction execution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clo ck division is used. figure 6-4 shows the parallel instruction fetches and instruction executions enabled by the har- vard architecture and the fast-access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the corr esponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 6-4. the parallel instruction fetches and instruction executions figure 6-5 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destina- tion register. figure 6-5. single cycle alu operation bit 151413121110 9 8 0x3e (0x5e) ? ? ? ? ? sp10 sp9 sp8 sph 0x3d (0x5d) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 00000000 00000000 clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3 rd instruction fetch 3 rd instruction execute 4th instruction fetch t1 t2 t 3 t4 cpu total execution time register operands fetch alu operation execute result write back t1 t2 t 3 t4 clk cpu 16 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 6.8 reset and inte rrupt handling the avr provides several different interrupt sources. these interrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in the status register in orde r to enable the interrupt. depending on the program counter value, interrupts may be automatically disabled when boot lock bits blb02 or blb12 are programmed. this feature improves software security. see the section ?memory program- ming? on page 283 for details. the lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 55 . the list also determines the priority levels of the different interrupts. the lower the address the higher is the priority level. reset has the highest priority, and next is int0 ? the external interrupt request 0. the interrupt vectors can be moved to the start of the boot flash section by setting the ivsel bit in the mcu control r egister (mcucr). refer to ?interrupts? on page 55 for more information. the reset vector can also be moved to the start of the boot flash section by programming the bootrst fuse, see ?boot loader support ? read- w hile- w rite self-programming? on page 266 . w hen an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are dis- abled. the user software can write logic one to the i-bit to enable nested interrupts. all enabled interrupts can then interrupt the current interrupt routine. the i-bit is automatically set when a return from interrupt instruction ? reti ? is executed. there are basically two types of interrupts. the fi rst type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the actual interrupt vec- tor in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt fl ag will be set and remember ed until the interrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt conditions occur while the global interrupt enable bit is clea red, the corres ponding interrupt fl ag(s) will be set and remembered until the global interrupt enable bit is set, and will then be exec uted by order of priority. the second type of interrupts will trigger as long as the interrupt condition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disappears before the interrupt is enabled, the in terrupt will not be triggered. w hen the avr exits from an interrupt, it will alwa ys return to the main program and execute one more instruction before any pending interrupt is served. note that the status register is not automatica lly stored when entering an interrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. w hen using the cli instruction to disable interrupts, the interrup ts will be immediately disabled. no interrupt will be executed af ter the cli instruction, even if it occurs simultaneously with the cli instruction. the following example shows how this can be used to avoid interrupts during the timed eeprom write sequence. 17 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 w hen using the sei instruction to enable interrupt s, the instruction following sei will be exe- cuted before any pending interrupts, as shown in this example. 6.8.1 interrupt response time the interrupt execution response for all the enabl ed avr interrupts is four clock cycles mini- mum. after four clock cycles the program vector address for the actual interrupt handling routine is executed. during this four clock cycle period, the program counter is pushed onto the stack. the vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. if an interrupt occurs during execution of a multi- cycle instruction, this in struction is completed before the interrupt is served. if an interrupt occurs when the mcu is in sleep mode, the interrupt execution response time is increased by four clock cycles. this increase comes in addition to the start-up time from the selected sleep mode. a return from an interrupt handling routine take s four clock cycles. during these four clock cycles, the program counter (two bytes) is popped back from the stack, the stack pointer is incremented by two, and the i-bit in sreg is set. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eemwe ; start eeprom write sbi eecr, eewe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ __disable_interrupt(); eecr |= (1< 19 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 7-1. program memory map 7.2 sram data memory figure 7-2 on page 20 shows how the sram memory is organized. the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. the lower 1,280/2,304/4,352 data memory locations address both the register file, the i/o memory, extended i/o memory, and the internal data sram. the first 32 locations address the register file, the next 64 location the standard i/o memory, then 160 locations of extended i/o memory, and the next 1024/2,048/4,096 locations address the internal data sram. the five different addressing modes for the data memory cover: direct, indirect with displace- ment, indirect, indirect with pre-decrement, and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode reaches 63 address locations from the base address given by the y- or z-register. w hen using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers x, y, and z are decremented or incremented. the 32 general purpose working registers, 64 i /o registers, 160 extended i/o registers, and the 1,024/2,048/4,096 bytes of internal data sram in the are all accessible through all these addressing modes. the register file is described in ?general purpose register file? on page 13 . 0x0000 0x1fff/0x3fff/0x7fff program memory application flash section boot flash section 20 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 7-2. data memory 7.2.1 data memory access times this section describes the general access timi ng concepts for internal memory access. the internal data sram access is performed in two clk cpu cycles as described in figure 7-3 on page 20 . figure 7-3. on-chip data sram access cycles 32 regi s ter s 64 i/o regi s ter s intern a l sram (1024 x 8) (2048 x 8) (4096 x 8) 0x0000 - 0x001f 0x0020 - 0x005f 0x04ff/0x08ff/0x10ff 0x0060 - 0x00ff data memory x 8 160 ext i/o reg. 0x0100 clk wr rd data data address address valid t1 t2 t 3 compute address read write cpu memory access instruction next instruction 21 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 7.3 eeprom data memory the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p contains 512 bytes of data eeprom memory. it is organized as a separ ate data space, in which single bytes can be read and written. the eeprom has an endur ance of at least 100,00 0 write/erase cycles. this section describes the a ccess between the eeprom and t he cpu, specifying the eeprom address registers, the eeprom data regi ster, and the eeprom control register. for a detailed description of spi, jtag and parallel data downloading to the eeprom, see ?serial downloading? on page 298 , ?programming via the jtag interface? on page 304 , and ?parallel programming parameters, pin mapping, and commands? on page 286 respectively. 7.3.1 eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access time for the eeprom is given in table 7-1 on page 22 . a self-timing function, however, lets the user software detect when the nex t byte can be written. if the user code con- tains instructions that write the eeprom, some precautions must be taken. in heavily filtered power supplies, v cc is likely to rise or fall slowly on power-up/down. this causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. see ?preventing eeprom corruption? on page 24 for details on how to avoid problems in these situations. in order to prevent unintentional eeprom writes, a specific write procedure must be followed. w hen the eeprom is read, the cpu is halted for four clock cycles before the next in struction is executed. w hen the eeprom is written, the cpu is halted for two clock cycles before the next instruction is executed. the following procedure sh ould be followed when writing the eeprom (the order of steps 3 and 4 is not essential). see ?register description? on page 26 for supplementary description for each register bit: 1. w ait until ee w e becomes zero. 2. w ait until spmen in spmcsr becomes zero. 3. w rite new eeprom address to eear (optional). 4. w rite new eeprom data to eedr (optional). 5. w rite a logical one to the eem w e bit while writing a zero to ee w e in eecr. 6. w ithin four clock cycles after setting eem w e, write a logical one to ee w e. the eeprom can not be programmed during a cpu write to the flash memory. the software must check that the flash programming is co mpleted before initiating a new eeprom write. step 2 is only relevant if the software contai ns a boot loader allowing the cpu to program the flash. if the flash is never being updated by the cpu, step 2 can be omitted. see ?boot loader support ? read- w hile- w rite self-programming? on page 266 for details about boot programming. caution: an interrupt between step 5 and step 6 will make the write cycle fail, since the eeprom master w rite enable will time-out. if an interrupt routine accessing the eeprom is interrupting another eeprom acce ss, the eear or eedr register will be modified, causing the interrupted eeprom access to fail. it is recommended to have the global interrupt flag cleared during all the steps to avoid these problems. 22 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 w hen the write access time has elapsed, the ee w e bit is cleared by hardware. the user soft- ware can poll this bit and wait for a zero before writing the next byte. w hen ee w e has been set, the cpu is halted for two cycles before the next instruction is executed. the user should poll the ee w e bit before starting the read operation. if a write operation is in progress, it is neither possi ble to read the eeprom, nor to change the eear register. the calibrated oscillator is used to time the eeprom accesses. table 7-1 lists the typical pro- gramming time for eeprom access from the cpu. note: 1. 3.3 applies to atmega165a/atmega165pa the following code examples show one assembly and one c function for writing to the eeprom. to avoid that interrupts will occur dur ing execution of these functions, the examples assume that interrupts are controlled (e.g. by disabling interrupts globally). the examples also assume that no flash boot loader is present in the software. if such code is present, the eeprom write function must also wait fo r any ongoing spm co mmand to finish. table 7-1. eeprom programming time symbol number of calibrated rc oscillator cycles ty pical programming time eeprom write (from cp u) 27 072 3.3/3.4ms (1) 23 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 the next code examples show assembly and c functions for reading the eeprom. the exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. assembly code example eeprom_write: ; wait for completion of previous write sbic eecr,eewe rjmp eeprom_write ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; write data (r16) to data register out eedr,r16 ; write logical one to eemwe sbi eecr,eemwe ; start eeprom write by setting eewe sbi eecr,eewe ret c code example void eeprom_write( unsigned int uiaddress, unsigned char ucdata) { /* wait for completion of previous write */ while(eecr & (1< 26 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 7.6 register description 7.6.1 eearh and eearl ? eeprom address register atmega 165a/atmega165pa ? bits 15:9 ? reserved these bits are reserved and will always read as zero. ? bits 8:0 ? eear8:0: eeprom address the eeprom address registers ? eearh and eearl specify the eeprom address in the 512 bytes eeprom space. the eeprom data bytes are ad dressed linearly between 0 and 511. the initial value of eear is undefined. a proper value must be written before the eeprom may be accessed. 7.6.2 eearh and eearl ? eeprom address registeratmega325a/325pa/3250a/3250pa/625a/645p/6450a/6450p ? bits 15:11 ? reserved these bits are reserved bits in the atmega325a/325pa/ 3250a/3250pa/645a/645p/6450a/6450 p and will always read as zero. ? bits 10:0 ? eear10:0: eeprom address the eeprom address registers ? eearh and eearl specify the eeprom address in the 1/2k bytes eeprom space. the eeprom data bytes are addressed linearly between 0 and 1023/2047. the initial value of eear is undefined. a proper valu e must be written before the eeprom may be accessed. note: 1. eear10 is only valid for atmega645a/atmega645p/atmega6450a/atmega6450p 7.6.3 eedr ? eeprom data register bit 151413121110 9 8 0x22 (0x42) ? ? ? ? ? ? ? eear8 eearh 0x21 (0x41) eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl 76543210 read/ w rite rrrrrrrr/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 x xxxxxxxx bit 1514131211 10 9 8 0x22 (0x42) ? ? ? ? ?eear10 (1) eear9 eear8 eearh 0x21 (0x41) eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl 76543 2 1 0 read/ w riterrrrrr/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 x x x xxxxx x x x bit 76543210 0x20 (0x40) msb lsb eedr read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 27 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 ? bits 7:0 ? eedr7:0: eeprom data for the eeprom write operation, the eedr register contains the data to be written to the eeprom in the address given by the eear regi ster. for the eeprom read operation, the eedr contains the data read out from the eeprom at the add ress given by eear. 7.6.4 eecr ? eeprom control register ? bits 7:4 ? reserved these bits are reserved and will always read as zero. ? bit 3 ? eerie: eeprom ready interrupt enable w riting eerie to one enables the eeprom ready interrupt if the i bit in sreg is set. w riting eerie to zero disables the interrupt. the eeprom ready interrupt generates a constant inter- rupt when ee w e is cleared. ? bit 2 ? eemwe: eeprom master write enable the eem w e bit determines whether setting ee w e to one causes the eeprom to be written. w hen eem w e is set, setting ee w e within four clock cycles w ill write data to the eeprom at the selected address. if eem w e is zero, setting ee w e will have no effect. w hen eem w e has been written to one by software, hardware clears th e bit to zero after four clock cycles. see the description of the ee w e bit for an eeprom write procedure. ? bit 1 ? eewe: eeprom write enable the eeprom w rite enable signal ee w e is the write strobe to the eeprom. w hen address and data are correctly set up, the ee w e bit must be written to one to write the value into the eeprom. the eem w e bit must be written to one before a logical one is written to ee w e, oth- erwise no eeprom write takes place. ? bit 0 ? eere: eeprom read enable the eeprom read enable signal eere is the read strobe to the eeprom. w hen the correct address is set up in the eear register, the eere bit must be written to a logic one to trigger the eeprom read. the eeprom read access takes one instruction, and th e requested data is available immediately. w hen the eeprom is read, the cpu is halted for four cycles before the next instruction is executed. 7.6.5 gpior2 ? general purpose i/o register 2 7.6.6 gpior1 ? general purpose i/o register 1 bit 765432 10 0x1f (0x3f) ? ? ? ? eerie eemwe eewe eere eecr read/ w rite rrrrr/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 x 0 bit 76543210 0x2b (0x4b) msb lsb gpior2 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x2a (0x4a) msb lsb gpior1 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 28 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 7.6.7 gpior0 ? general purpose i/o register 0 bit 76543210 0x1e (0x3e) msb lsb gpior0 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 29 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 8. system clock and clock options 8.1 clock systems and their distribution figure 8-1 on page 29 presents the principal clock systems in the avr and their distribution. all of the clocks need not be active at a given time. in order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ?power management and sleep modes? on page 39 . the clock systems are detailed below. figure 8-1. clock distribution 8.1.1 cpu clock ? clk cpu the cpu clock is routed to parts of the system concerned with operation of the avr core. examples of such modules are the general pur pose register file, the status register and the data memory holding the stack pointer. halting the cpu clock inhibits the core from performing general operations and calculations. 8.1.2 i/o clock ? clk i/o the i/o clock is used by the majority of the i/o modules, like timer/counters, spi, and usart. the i/o clock is also used by the external inte rrupt module, but note that some external inter- rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the i/o clock is halted. also note that start condition detection in the usi module is carried out asynchro- nously when clk i/o is halted, enabling usi start cond ition detection in all sleep modes. 8.1.3 flash clock ? clk flash the flash clock controls operation of the flash in terface. the flash clock is usually active simul- taneously with the cpu clock. general i/o modules asynchronous timer/counter cpu core ram clk i/o clk a s y avr clock control unit clk cpu flash and eeprom clk fla s h s ource clock watchdog timer watchdog oscillator reset logic clock multiplexer watchdog clock calibrated rc oscillator timer/counter oscillator crystal oscillator low-frequency crystal oscillator external clock s ystem clock prescaler 30 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 8.1.4 asynchronous timer clock ? clk asy the asynchronous timer clock al lows the asynchronous timer/c ounter to be clocked directly from an external clock or an external 32khz clock crystal. the dedicated clock domain allows using this timer/counter as a real-time counter even when the device is in sleep mode. 8.1.5 adc clock ? clk adc the adc is provided with a dedicated clock domain. this allows halting the cpu and i/o clocks in order to reduce noise generated by digital circuitry. this gives more accurate adc conversion results. 8.2 clock sources the device has the following clock source options, selectable by flash fuse bits as shown below. the clock from the selected source is input to the avr clock generator, and routed to the appropriate modules. note: 1. for all fuses ?1? means unprogrammed while ?0? means programmed. the various choices for each clocking opti on is given in the following sections. w hen the cpu wakes up from power-down or power-save, the selected clock source is used to time the start- up, ensuring stable osc illator operation bef ore instruction execution starts. w hen the cpu starts from reset, there is an additional delay allowi ng the power to reach a stable level before com- mencing normal operation. the w atchdog oscillator is used for timing this real-time part of the start-up time. the number of w dt oscillator cycles used for each time-out is shown in table 8- 2 . the frequency of the w atchdog oscillator is voltag e dependent as shown in ?typical charac- teristics? on page 332 . table 8-1. device clocking options select (1) device clocking option cksel3:0 external crystal/ceramic resonator 1111 - 1000 external low-frequency crystal 0111 - 0110 calibrated internal rc oscillator 0010 external clock 0000 reserved 0011, 0001, 0101, 0100 table 8-2. number of w atchdog oscillator cycles typ time-out (v cc = 5.0v) typ time-out (v cc = 3.0v) number of cycles 4.1ms 4.3ms 4k (4,096) 65ms 69ms 64k (65,536) 31 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 8.3 default clock source the device is shipped with cksel = ?0010?, sut = ?10?, and ckdiv8 programmed. the default clock source setting is the internal rc oscillator with longes t start-up time and an initial system clock prescaling of 8. this default setting ensures that all users can make their desired clock source setting using an in-system or parallel programmer. 8.4 calibrated internal rc oscillator by default, the internal rc o scillator provides an approximate 8mhz clock. though voltage and temperature dependent, this clock can be very accurately calibrated by the user. see table 27- 11 on page 325 and ?internal oscillator sp eed? on page 356 for more details. the device is shipped with the ckdiv8 fuse programmed. see ?system clock prescaler? on page 36 for more details. this clock may be selected as the system clock by programming the cksel fuses as shown in table 8-3 . if selected, it will operate with no external comp onents. during rese t, hardware loads the pre-programmed calibration value into the osccal register and thereby automatically cali- brates the rc oscillator. the accuracy of this calibration is shown as factory calibration in table 27-11 on page 325 . by changing the osccal register from s w , see ?osccal ? oscillator ca libration register? on page 37 , it is possible to get a higher calibration accuracy than by using the factory calibration. the accuracy of this calibration is shown as user calibration in table 27-11 on page 325 . w hen this oscillator is used as the chip clock, the w atchdog oscillator will still be used for the w atchdog timer and for the reset time-out. for more information on the pre-programmed cali- bration value, see the section ?calibration byte? on page 286 . notes: 1. the device is shipped with this option selected. 2. the frequency ranges are preliminary values. 3. if 8mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8. w hen this oscillator is selected, start-up times are determined by the sut fuses as shown in table 8-4 note: 1. the device is shipped with this option selected . table 8-3. internal calibrated rc o scillator operating modes (1)(3) frequency range (2) (mhz) cksel3:0 7.3 - 8.1 0010 table 8-4. start-up times for the internal calib rated rc oscillator clock selection power conditions start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) sut1:0 bod enabled 6 ck 14ck 00 fast rising power 6 ck 14ck + 4.1ms 01 slowly rising power 6 ck 14ck + 65ms (1) 10 reserved 11 32 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 8.5 crystal oscillator xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be con- figured for use as an on-chip oscillator, as shown in figure 8-2 . either a quartz crystal or a ceramic resonator may be used. c1 and c2 should always be equal for both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. some initial guidelines for choosing capacitors for use with crystals are given in table 8-5 . for ceramic resonators, the capacitor values given by the manufacturer should be used. figure 8-2. crystal oscillator connections the oscillator can operate in three different mo des, each optimized for a specific frequency range. the op erating mode is selected by t he fuses cksel3:1 as shown in table 8-5 . notes: 1. this option should not be used with crystals, only with ceramic resonators. the cksel0 fuse together with the sut1:0 fuses select the start-up times as shown in table 8-6 . table 8-5. crystal oscillator operating modes cksel3:1 frequency range (mhz) recommended range for capacitors c1 and c2 for use with crystals (pf) 100 (1) 0.4 - 0.9 ? 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 12 - 22 table 8-6. start-up times for the crysta l oscillator clock selection cksel0 sut1:0 start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) recommended usage 0 00 258 ck (1) 14ck + 4.1ms ceramic resonator, fast rising power 0 01 258 ck (1) 14ck + 65ms ceramic resonator, slowly rising power 010 1k ck (2) 14ck ceramic resonator, bod enabled xtal2 (to s c2) xtal1 (to s c1) gnd c2 c1 33 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 notes: 1. these options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start- up is not important for the application. these options are not suitable for crystals. 2. these options are intended for use with cerami c resonators and will ensure frequency stability at start-up. they can also be used with crystal s when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. 8.6 low-frequency crystal oscillator the low-frequency crystal osc illator is optimized for use wit h a 32.768khz watch crystal. w hen selecting crystals, load capacitance and crystal? s equivalent series resistance, esr must be taken into consideration. both values are specified by the crystal vendor. atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p oscillator is opti- mized for very low power consumption, and thus when selecting crystals, see table 8-7 for maximum esr recommendations on 9pf and 6.5pf crystals. note: 1. maximum esr is typical value based on characterization the low-frequency crystal oscillator provi des an internal load capacitance, see table 8-9 on page 34 at each tosc pin. atmega325a/325pa/3250a/3250pa/645a/645p/6450a/6450p oscillator is optimized for very low power consumption, and thus when selecting crystals, see table 8-8 on page 34 for maxi- mum esr recommendations on 6.5 pf, 9.0 pf and 12.5 pf crystals. 011 1k ck (2) 14ck + 4.1ms ceramic resonator, fast rising power 100 1k ck (2) 14ck + 65ms ceramic resonator, slowly rising power 1 01 16k ck 14ck crystal oscillator, bod enabled 1 10 16k ck 14ck + 4.1ms crystal oscillator, fast rising power 1 11 16k ck 14ck + 65ms crystal oscillator, slowly rising power table 8-6. start-up times for the crystal osc illator clock select ion (continued) cksel0 sut1:0 start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) recommended usage table 8-7. maximum esr recommendation for 32.768khz w atch crystal atmega165a/atmega165pa crystal cl (pf) max esr [k ] (1) 6.5 60 935 34 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 table 8-8. maximum esr recommendation for 32.768khz w atch crystal atmega325a/325pa/3250a/3250pa/645a/645p/6450a/6450p note: 1. maximum esr is typical value based on characterization the capacitance (ce + ci) needed at each tosc pin can be calculated by using: where: ce - is optional external capacitors as described in figure 8-2 on page 32 ci - is the pin capacitance in table 8-9 on page 34 cl - is the load capacitance for a 32.768khz crystal specified by the crystal vendor. c s - is the total stray capacitance for one tosc pin. crystals specifying load capacitance (cl) higher than the ones given in the table 8-9 on page 34 , require external capacitors applied as described in figure 8-2 on page 32 . the low-frequency crystal oscillato r must be selected by setting the cksel fuses to ?0110? or ?0111? as shown in table 8-11 . start-up times are determined by the sut fuses as shown in table 8-10 . note: 1. this option should only be used if frequen cy stability at start-up is not important for the application crystal cl (pf) max esr [k ] (1) 6.5 75 9.0 65 12.5 30 table 8-9. capacitance for low-freq uency crystal oscillator device 32khz osc. type cap (xtal1/tosc1) cap (xtal2/tosc2) atmega165a/165pa/325a/325pa/3250a/ 3250pa/645a/645p/6450a/6450p system osc. 16pf 6pf timer osc. 16pf 6pf table 8-10. start-up times for the lo w-frequency crystal os cillator clock selection sut1..0 additional delay from reset (v cc = 5.0v) recommended usage 00 14 ck fast rising power or bod enabled 01 14 ck + 4ms slowly rising power 10 14 ck + 65ms stable frequency at start-up 11 reserved table 8-11. start-up times for the lo w-frequency crystal os cillator clock selection cksel3... 0 start-up time from power-down and power-save recommended usage 0110 (1) 1k ck 0111 32k ck stable frequency at start-up ce ci + 2 cl ? c s ? = 35 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 8.7 external clock to drive the device from an external clock source, xtal1 should be driven as shown in figure 8-3 . to run the device on an ex ternal clock, the cksel fuses must be programmed to ?0000?. figure 8-3. external clock drive configuration w hen this clock source is selected, start-up ti mes are determined by the sut fuses as shown in table 8-13 . w hen applying an external clock, it is required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the mcu. a variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. it is required to en sure that the mcu is kept in reset during such changes in the clock frequency. note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still ensuri ng stable operation. refer to ?system clock prescaler? on page 36 for details. table 8-12. crystal oscillator clock frequency cksel3...0 frequency range atmega 165a/165pa/645a/645p 0000 0 - 16mhz atmega325a/325pa/3250a/3250pa /6450a/6450p 0000 0 - 20mhz table 8-13. start-up times for the external clock selection sut1..0 start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) recommended usage 00 6 ck 14ck bod enabled 01 6 ck 14ck + 4.1ms fast rising power 10 6 ck 14ck + 65ms slowly rising power 11 reserved nc external clock s ignal xtal2 xtal1 gnd 36 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 8.8 timer/counter oscillator atmega169p uses the same crystal oscillator for low-frequency oscilla tor and timer/counter oscillator. see ?low-frequency crystal oscillator? on page 33 for details on the oscillator and crystal requirements. atmega169p share the timer/counter oscilla tor pins (tosc1 and tosc2) with xtal1 and xtal2. w hen using the timer/counter oscillator, the system clock needs to be four times the oscillator frequency. due to this and the pin shar ing, the timer/counter oscillator can only be used when the calibrated internal rc oscilla tor is selected as system clock source. applying an external clock source to tosc1 c an be done if extclk in the assr register is written to logic one. see ?asynchronous operation of the timer/counter? on page 151 for further description on selecting external clock as input instead of a 32.768khz watch crystal. 8.9 clock output buffer w hen the ckout fuse is prog rammed, the system clock will be ou tput on clko. this mode is suitable when chip clock is used to drive other circuits on the system. the clock will be output also during reset and the normal operation of i/o pin will be over ridden when the fuse is pro- grammed. any clock source, including inter nal rc oscillator, can be selected when clko serves as clock output. if the system clock prescaler is used, it is the divided system clock that is output when the ckout fuse is programmed. 8.10 system clock prescaler the atmega165a/165 pa/325a/325pa/3250a/32 50pa/645a/645p/6450a /6450p system clock can be divided by setting the ?clkpr ? clock prescale register? on page 37 . this feature can be used to decrease the system clock frequency and power consumption when the requirement for processing power is low. this can be used with all clock sour ce options, and it will affect the clock frequency of the cpu and all synchronous peripherals. clk i/o , clk adc , clk cpu , and clk flash are divided by a factor as shown in table 8-14 . 8.10.1 switching time w hen switching between prescaler settings, the system clock prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. the ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the cpu?s clock frequency. hence, it is not possible to determine the state of the prescaler ? even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted. from the time the clkps values ar e written, it takes between t1 + t2 and t1 + 2*t2 before the new clock frequency is active. in this interval, 2 active clock edges are produced. here, t1 is the previous clock period, and t2 is the period corresponding to the new prescaler setting. 37 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 8.11 register description 8.11.1 osccal ? oscillato r calibration register ? bits 7:0 ? cal7:0: oscillator calibration value the oscillator calibration register is used to trim the calibrated internal rc oscillator to remove process variations from the oscillator frequency. a pre-programmed calibration value is automatically written to this register during chip reset, giving the factory calibrated frequency as specified in table 27-11 on page 325 . the application software can write this register to change the oscillator frequency. the os cillator can be calibrated to frequencies as specified in table 27- 11 on page 325 . calibration outside that range is not guaranteed. note that this o scillator is used to time eeprom and flash write accesses , and these write times will be affected accordingly. if the eeprom or flash are writ ten, do not calibrate to more than 8.8mhz. otherwise, the eeprom or flash write may fail. the cal7 bit determines the range of operation for the oscillator. setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. the two fre- quency ranges are overlapping, in other words a setting of osccal = 0x7f gives a higher frequency than osccal = 0x80. the cal6:0 bits are used to tune the frequency within the selected range. a setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7f gives the highest frequency in the range. 8.11.2 clkpr ? clock prescale register ? bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be written to logic one to enab le change of the clkps bits. the clkpce bit is only updated when the other bits in cl kpr are simultaneously wr itten to zero. clkpce is cleared by hardware four cycles af ter it is written or when clkps bits are written. rewriting the clkpce bit within this time-out period does neither extend the time-out period, nor clear the clkpce bit. ? bits 3:0 ? clkps3:0: clock prescaler select bits 3 - 0 these bits define the division factor between the selected clock source and the internal system clock. these bits can be written run-time to vary the clock frequency to suit the application requirements. as the divider divides the master clock input to the mcu, the speed of all synchro- nous peripherals is reduced when a division fact or is used. the division factors are given in table 8-14 . bit 76543210 (0x66) cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value device specific calibration value bit 76543210 (0x61) clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 clkpr read/ w rite r/ w rrrr/ w r/ w r/ w r/ w initial value 0 0 0 0 see bit description 38 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 to avoid unintentional changes of clock frequency, a special write procedure must be followed to change the clkps bits: 1. w rite the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. w ithin four cycles, write the desired valu e to clkps while writing a zero to clkpce. interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. the ckdiv8 fuse determines the initial value of the clkps bits. if ckdiv8 is unprogrammed, the clkps bits will be reset to ?0000?. if ckdiv8 is programmed, clkps bits are reset to ?0011?, giving a division factor of 8 at start up. this feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operat- ing conditions. note that any value can be written to the clkps bits regardless of the ckdiv8 fuse setting. the application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. the device is shipped with the ckdiv8 fuse programmed. table 8-14. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved 39 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 9. power management and sleep modes 9.1 overview sleep modes enable the application to shut down unused modules in the mcu, thereby saving- power. the avr provides various sleep modes allowing the user to tailor the power consumption to the application?s requirements. 9.2 sleep modes figure 8-1 on page 29 presents the different clock systems in the atmega165a/165pa/325a/325pa/3250a/3250pa/ 645a/645p/6450a/6450p, and their distribu- tion. the figure is helpful in selecting an appropriate sleep mode. table 9-1 shows the different sleep modes and their wake up sources and bod disable ability (1) . note: 1. bod disable is only available for atmega165pa/325pa/3250pa/645p/6450p notes: 1. only recommended with external crystal or resonator selected as clock source. 2. if timer/counter2 is running in asynchronous mode. 3. for int0, only level interrupt. to enter any of the sleep modes, the se bit in smcr must be written to logic one and a sleep instruction must be executed. the sm2, sm1, and sm0 bits in the smcr register select which sleep mode will be activated by the sleep instruction. see table 9-2 on page 44 for a summary. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up. the mcu is then halted for four cycles in addition to the st art-up time, executes the interrupt routine, and resumes execution from the instruction followi ng sleep. the contents of the register file and sram are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. 9.3 bod disable (1) w hen the brown-out detector (bod) is enabled by bodlevel fuses - see table 27-7 on page 322 and onwards, the bod is actively monitoring the power supply voltage during a sleep period. to save power, it is possible to disable the bod by software for some of the sleep- modes, see table 9-1 on page 39 . the sleep mode power consum ption will then be at the same level as when bod is globally disabled by fuses. if bod is disabled in software, the bod func- table 9-1. active clock domains and w ake-up sources in the different sleep modes. active clock domains oscillators wake-up sources software bod disable sleep mode clk cpu clk flash clk io clk adc clk asy main clock source enabled timer osc enabled int0 and pin change usi start condition timer2 spm/ eeprom ready adc otheri/o idle xxx x x (2) xxxxx x adc nrm x x x x (2) x (3) xx (2) xx power-down x (3) xx power-save x x x (3) xx x standby (1) xx (3) xx 40 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 tion is turned off immediately after entering the sleep mode. upon wake-up from sleep, bod is automatically enabled again. this ensures safe operation in case the vcc level has dropped during the sleep period. w hen the bod has been disabled, the wake-up time from sle ep mode will be ap proximately 60 s to ensure that the bod is working correctl y before the mcu continues executing code. bod disable is controlled by bit 6, bods (bod sleep) in the control register mcucr, see ?mcucr ? mcu control register? on page 61 . w riting this bit to one turns off the bod in relevant sleep modes, while a zero in this bit keeps bod acti ve. default setting keeps bod active, i.e. bods set to zero. w riting to the bods bit is controlled by a timed sequence and an enable bit, see ?mcucr ? mcu control register? on page 61 . note: 1. bod disable only available in picopower devices atmega165pa/325pa/3250pa/645p/6450p. 9.4 idle mode w hen the sm2:0 bits are written to 000, the sleep instruction makes the mcu enter idle mode, stopping the cpu but allowing the spi, usart, analog comparator, adc, usi, timer/coun- ters, w atchdog, and the interrupt system to continue operating. this sleep mode basically halts clk cpu and clk flash , while allowing the other clocks to run. idle mode enables the mcu to wake up from external triggered interrupts as well as internal ones like the timer overflow and usart transmit complete interrupts. if wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the acd bit in the analog comparator control and status regist er ? acsr. this will reduce power consumption in idle mode. if t he adc is enabled, a conversion starts automati- cally when this mode is entered. 9.5 adc noise reduction mode w hen the sm2:0 bits are written to 001, th e sleep instruction makes the mcu enter adc noise reduction mode, stopping the cpu but allowi ng the adc, the external interrupts, the usi start condition detection, timer/counter2, and the w atchdog to continue operating (if enabled). this sleep mode basically halts clk i/o , clk cpu , and clk flash , while allowing the other clocks to run. this improves the noise environment for the ad c, enabling higher resolution measurements. if the adc is enabled, a conversion starts automatically when this mode is entered. apart form the adc conversion complete interrupt, only an external reset, a w atchdog reset, a brown-out reset, usi start condition interrupt, a timer/counter2 interrupt, an spm/eeprom ready inter- rupt, an external level interrupt on int0 or a pin change interrupt can wake up the mcu from adc noise reduction mode. 9.6 power-down mode w hen the sm2:0 bits are written to 010, the sleep instruction makes the mcu enter power- down mode. in this mode, the external oscillator is stopped, while the external interrupts, the usi start condition detection, and the w atchdog continue operating (i f enabled). only an exter- nal reset, a w atchdog reset, a brown-out reset, usi start condition interrupt, an external level interrupt on int0, or a pin change interrupt can wake up the mcu. this sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some time to wake up the mcu. refer to ?external interrupts? on page 62 for details. 41 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 w hen waking up from power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stable after having been stopped. the wake-up period is defined by the same cksel fuses that define the reset time-out period, as described in ?clock sources? on page 30 . 9.7 power-save mode w hen the sm2:0 bits are written to 011, the sleep instruction makes the mcu enter power- save mode. this mode is identical to power-down, with one exception: if timer/counter2 is e nabled, it will keep running during sleep. the device can wake up from either timer overflow or output compare event from timer/counter2 if the corresponding timer/counter2 interrupt enable bits are set in timsk2, and the global interrupt enable bit in sreg is set. if timer/counter2 is not enabled, power-down mode is recommended instead of power-save mode. the timer/counter2 can be clocked both synchronously and asynchronously in power-save mode. the clock source for the two modules can be selected independent of each other. if the timer/counter2 is not using the asynchronous cl ock, the timer/counter oscillator is stopped during sleep. if the timer/counter2 is not us ing the synchronous clock, the clock source is stopped during sleep. note that even if the synchronous clock is running in power-save, this clock is only available for timer/counter2. 9.8 standby mode w hen the sm2:0 bits are 110 and an external crystal/resonator clock option is selected, the sleep instruction makes the mcu enter standby mode. this mode is identical to power-down with the exception that the oscillator is kept running. fr om standby mode, the device wakes up in six clock cycles. 9.9 power reduction register the power reduction register (prr), see ?prr ? power reduction register? on page 45 , pro- vides a method to stop the clock to individual per ipherals to reduce power consumption. the current state of the peripheral is frozen and the i/o registers can not be read or written. resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. w aking up a module, which is done by clearing the bit in prr, puts the module in the same state as before shutdown. module shutdown can be used in idle mode and ac tive mode to significantly reduce the overall power consumption. see ?atmega165a: supply current of i/o modules? on page 337 for exam- ples. in all other sleep modes, the clock is already stopped. 9.10 minimizing po wer consumption there are several issues to consider when trying to minimize the power consumption in an avr controlled system. in general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possi ble of the device?s functions are operating. all functions not needed should be disabled. in particular, the following modules may need special consideration when trying to achieve th e lowest possible power consumption. 9.10.1 analog to digital converter if enabled, the adc will be enabled in all sleep modes. to save power, the adc should be dis- abled before entering any sleep mode. w hen the adc is turned off and on again, the next 42 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 conversion will be an exte nded conversion. refer to ?adc - analog to digital converter? on page 214 for details on adc operation. 9.10.2 analog comparator w hen entering idle mode, the analog comparator should be disabled if not used. w hen entering adc noise reduction mode, the analog comparator should be disabled. in other sleep modes, the analog comparator is automatically disabled. however, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in all sleep modes. otherwise, the internal voltage reference will be enabled, independent of sleep mode. refer to ?ac - analog comparator? on page 210 for details on how to configure the ana- log comparator. 9.10.3 brown-out detector if the brown-out detector is not needed by the application, this module should be turned off. if the brown-out detector is enabled by the bo dlevel fuses, it will be enabled in all sleep modes, and hence, always co nsume power. in the deeper sleep modes, this w ill contribute sig- nificantly to the total current consumption. refer to ?brown-out detect ion? on page 49 for details on how to configure the brown-out detector. 9.10.4 internal voltage reference the internal voltage referenc e will be enabled when needed by the brown-out de tection, the analog comparator or the adc. if these modules are disabled as described in the sections above, the internal voltage re ference will be disabled and it will not be consuming power. w hen turned on again, the user must allow the reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to ?internal volt- age reference? on page 50 for details on the start-up time. 9.10.5 watchdog timer if the w atchdog timer is not needed in the application, the module should be turned off. if the w atchdog timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. in the deeper slee p modes, this will contribute signific antly to the total current consump- tion. refer to ? w atchdog timer? on page 50 for details on how to configure the w atchdog timer. 9.10.6 port pins w hen entering a sleep mode, all port pins should be configured to use minimum power. the most important is then to ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buf fers of the device will be disabled. this ensures that no power is consumed by the input logic when not needed. in some cases, the input logic is needed for detec ting wake-up conditions, and it will then be enabled. refer to the section ?digital input enable and sleep modes? on page 72 for details on which pins are enabled. if the input buffer is enabl ed and the input signal is left floating or have an analog signal level close to v cc /2, the input buffer will use excessive power. for analog input pins, the digital input buffer should be disabled at all times. an analog signal level close to v cc /2 on an input pin can cause significant current even in active mode. digital input buffers can be disabled by writing to the digital input disable registers (didr1 and didr0). refer to ?didr1 ? digital input disable register 1? on page 213 and ?didr0 ? digital input disable register 0? on page 231 for details. 43 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 9.10.7 jtag interface and on-chip debug system if the on-chip debug system is enabled by the ocden fuse and the chip enter power down or power save sleep mode, the main clock source remains enabled. in these sl eep modes, this will contribute significantly to the total current c onsumption. there are three alternative ways to avoid this: ? disable ocden fuse. ? disable jtagen fuse. ? w rite one to the jtd bit in mcucr. the tdo pin is left floating when the jtag interf ace is enabled while th e jtag tap controller is not shifting data. if the hardware connected to t he tdo pin does not pull up the logic level, power consumption will increase. note that the tdi pin fo r the next device in the scan chain con- tains a pull-up that avoids this problem. w riting the jtd bit in the mcucr register to one or leaving the jtag fuse unprogrammed disables the jtag interface. 44 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 9.11 register description 9.11.1 smcr ? sleep mode control register the sleep mode control register contains control bits for power management. ? bits 3, 2, 1 ? sm2:0: sleep mode select bits 2, 1, and 0 these bits select between the five available sleep modes as shown in table 9-2 . note: 1. standby mode is only recommended for use with external crystals or resonators. ? bit 0 ? se: sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu enteri ng the sleep mode unless it is the programmer?s purpose, it is recommended to write the sleep enable (se) bit to one just before the execution of the sleep instruction and to clear it immediately af ter waking up. 9.11.2 mcucr ? mcu control register note: 1. only available in the picopower devices atmega165pa/325pa/3250pa/645p/6450p. ? bit 6 ? bods: bod sleep the bods bit must be written to logic one in order to turn off bod during sleep, see table 9-1 on page 39 . w riting to the bods bit is controlled by a timed sequence and an enable bit, bodse in mcucr. to disable bo d in relevant sleep modes, both bods and bodse must first be set to one. then, to set the bods bit, bods must be set to one and bodse must be set to zero within four clock cycles. bit 76543210 0x33 (0x53) ? ? ? ? sm2 sm1 sm0 se smcr read/ w rite rrrrr/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 table 9-2. sleep mode select sm2 sm1 sm0 sleep mode 000idle 0 0 1 adc noise reduction 0 1 0 power-down 0 1 1 power-save 100reserved 101reserved 1 1 0 standby (1) 111reserved bit 7 6 5 4 3 2 1 0 0x35 (0x55) jtd bods (1) bodse (1) pud ? ? ivsel ivce mcucr read/ w rite r/ w r/ w r/ w r/ w rrr/ w r/ w initial value 0 0 0 0 0 0 0 0 45 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 the bods bit is active three clock cycles after it is set. a sleep instruction must be executed while bods is active in order to turn off the bod for the actual sleep mode. the bods bit is automatically cleared after three clock cycles. ? bit 5 ? bodse: bod sleep enable bodse enables setting of bods control bit, as ex plained in bods bit description. bod disable is controlled by a timed sequence. 9.11.3 prr ? power reduction register ? bit 7:4 - reserved these bits are reserved and will always read as zero. ? bit 3 - prtim1: power reduction timer/counter1 w riting a logic one to this bit shuts down the timer/counter1 module. w hen the timer/counter1 is enabled, operation will cont inue like before the shutdown. ? bit 2 - prspi: power reduction serial peripheral interface w riting a logic one to this bit shuts down the seri al peripheral interface by stopping the clock to the module. w hen waking up the spi again, the spi should be re initialized to ensure proper operation. ? bit 1 - prusart0: power reduction usart0 w riting a logic one to this bit shuts down th e usart by stopping the clock to the module. w hen waking up the usart again, the usart should be re initialized to ensure proper operation. ? bit 0 - pradc: power reduction adc w riting a logic one to this bit shuts down the adc. the adc must be disabled before shut down. the analog comparator cannot use the adc input mux when the adc is shut down. note: the analog comparator is disabled using the acd-bit in the ?acsr ? analog comparator control and status register? on page 212 . bit 7 6 5 4 3 2 1 0 (0x64) ? ? ? ? prtim1 prspi prusart0 pradc prr read/ w rite r r r r r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 46 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 10. system control and reset 10.1 resetting the avr during reset, all i/o registers are set to their initial values, and the program starts execution from the reset vector. the instruction placed at the reset vector must be a jmp ? absolute jump ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the app lication section while the interrupt vectors are in the boot section or vice versa. the circuit diagram in figure 10-1 on page 47 shows the reset logic. table 27-13 on page 326 defines the electrical parameters of the reset circuitry. the i/o ports of the avr are immediately reset to their initial state when a reset source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. this allows the power to reach a stable level before normal operation starts. the time-out period of the delay counter is defined by the user through the sut and cksel fuses. the dif- ferent selections for the delay period are presented in ?clock sources? on page 30 . 10.2 reset sources the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p has five sources of reset: ? power-on reset. the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). ? external reset. the mcu is reset when a low level is present on the reset pin for longer than the minimum pulse length. ? w atchdog reset. the mcu is reset when the w atchdog timer period expires and the w atchdog is enabled. ? brown-out reset. the mcu is reset when the supply voltage v cc is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. ? jtag avr reset. the mcu is reset as long as there is a logic one in the reset register, one of the scan chains of the jtag system. refer to the section ?ieee 1149.1 (jtag) boundary- scan? on page 239 for details. 47 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 10-1. reset logic 10.2.1 power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detection level is defined in ?system and reset characteristics? on page 326 . the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as to detect a fa ilure in supply voltage. a power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes the delay counter, which determines how long the device is kept in reset after v cc rise. the reset signal is acti vated again, without any delay, when v cc decreases below the detection level. figure 10-2. mcu start-up, reset tied to v cc mcu s tatus register (mcu s r) brown-out reset circuit bodlevel [2..0] delay counters ck s el[ 3 :0] ck timeout wdrf borf extrf porf data b u s clock generator s pike filter pull-up resistor jtrf jtag reset register watchdog oscillator s ut[1:0] power-on reset circuit v re s et time-out internal re s et t tout v pot v r s t cc 48 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 10-3. mcu start-up, reset extended externally 10.2.2 external reset an external reset is generated by a low level on the reset pin. reset pulses longer than the minimum pulse width (see ?system and reset characteristics? on page 326 ) will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. w hen the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. figure 10-4. external reset during operation re s et time-out internal re s et t tout v pot v r s t v cc cc 49 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 10.2.3 brown-out detection atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p has an on-chip brown-out detection (bod) circuit for monitoring the v cc level during operation by comparing it to a fixed trigger level. the tr igger level for the bod can be selected by the bodlevel fuses. the trigger level has a hysteresis to ensure spike free brown-out detection. the hysteresis on the detection level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2. w hen the bod is enabled, and v cc decreases to a value below the trigger level (v bot- in figure 10-5 ), the brown-out reset is immediately activated. w hen v cc increases above the trigger level (v bot+ in figure 10-5 ), the delay counter starts the mcu after the time-out period t tout has expired. the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for lon- ger than t bod given in ?system and reset characteristics? on page 326 . figure 10-5. brown-out reset during operation 10.2.4 watchdog reset w hen the w atchdog times out, it will gene rate a short reset pulse of one ck cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to page 50 for details on operation of the w atchdog timer. figure 10-6. w atchdog reset during operation v cc re s et time-out internal re s et v bot- v bot+ t tout ck cc 50 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 10.3 internal voltage reference atmega165a/165pa/325a/325pa/3250a/3250pa/ 645a/645p/6450a/6450p features an inter- nal bandgap reference. this reference is used for brown-out detection, and it can be used as an input to the analog comparator or the adc. 10.3.1 voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the start-up time is given in ?system and reset characteristics? on page 326 . to save power, the reference is not always turned on. the reference is on during the following situations: 1. w hen the bod is enabled (by progra mming the bodlevel [2...0] fuse). 2. w hen the bandgap reference is connected to the analog comparator (by setting the acbg bit in acsr). 3. w hen the adc is enabled. thus, when the bod is not enabled, after setting the acbg bit or enabling the adc, the user must always allow the reference to start up before the output from the analog comparator or adc is used. to reduce power consumption in power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering power-down mode. 10.4 watchdog timer the w atchdog timer is clocked from a separate on-chip oscillator which runs at 1 mhz. this is the typical value at v cc = 5v. see characterization data for typical values at other v cc levels. by controlling the w atchdog timer prescaler, the w atchdog reset interval can be adjusted as shown in table 10-2 on page 54 . the w dr ? w atchdog reset ? instruction resets the w atch- dog timer. the w atchdog timer is also reset when it is disabled and when a chip reset occurs. eight different clock cycle periods can be selected to determine the reset period. if the reset period expires without another w atchdog reset, the atmega165a/165pa/325a/325pa/3250a/3250pa/ 645a/645p/6450a/6450p resets and exe- cutes from the reset vector. for timing details on the w atchdog reset, refer to table 10-2 on page 54 . to prevent unintentional disabling of the w atchdog or unintentional change of time-out period, two different safety levels are selected by the fuse w dton as shown in table 10-1. refer to ?timed sequences for changing the configuration of the w atchdog timer? on page 51 for details. table 10-1. w dt configuration as a function of the fuse settings of w dton wdton safety level wdt initial state how to disable the wdt how to change time- out unprogrammed 1 disabled timed sequence timed sequence programmed 2 enabled always enabled timed sequence 51 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 10-7. w atchdog timer 10.4.1 timed sequences for changing the configuration of the watchdog timer the sequence for changing configuration differs slightly between the two safety levels. separate procedures are described for each level. 10.4.1.1 safety level 1 in this mode, the w atchdog timer is initially disabled , but can be enabled by writing the w de bit to 1 without any restriction. a timed sequence is needed when changing the w atchdog time-out period or disabling an enabled w atchdog timer. to disable an enabled w atchdog timer, and/or changing the w atchdog time-out, the following procedure must be followed: 1. in the same operation, write a logic one to w dce and w de. a logic one must be written to w de regardless of the previous value of the w de bit. 2. w ithin the next four clock cycles, in the same operation, write the w de and w dp bits as desired, but with the w dce bit cleared. 10.4.1.2 safety level 2 in this mode, the w atchdog timer is always enabled, and the w de bit will always read as one. a timed sequence is needed when changing the w atchdog time-out period. to change the w atchdog time-out, the following procedure must be followed: 1. in the same operation, write a logical one to w dce and w de. even though the w de always is set, the w de must be written to one to start the timed sequence. w ithin the next four clock cycles, in the same operation, write the w dp bits as desired, but with the w dce bit cleared. the value written to the w de bit is irrelevant. watchdog o s cillator 52 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 note: 1. see ?about code examples? on page 9 . assembly code example (1) wdt_off: ; reset wdt wdr ; write logical one to wdce and wde in r16, wdtcr ori r16, (1< 54 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 ? bit 3 ? wde: watchdog enable w hen the w de is written to logic one, the w atchdog timer is enabled, and if the w de is written to logic zero, the w atchdog timer function is disabled. w de can only be cleared if the w dce bit has logic level one. to disable an enabled w atchdog timer, the following procedure must be followed: 1. in the same operation, write a logic one to w dce and w de. a logic one must be written to w de even though it is set to one before the disable operation starts. 2. w ithin the next four clock cycles, write a logic 0 to w de. this disables the w atchdog. in safety level 2, it is not possible to disable the w atchdog timer, even with the algorithm described above. see ?timed sequences for changing the configuration of the w atchdog timer? on page 51. ? bits 2:0 ? wdp2, wdp1, wdp0: watchdog timer prescaler 2, 1, and 0 the w dp2, w dp1, and w dp0 bits determine the w atchdog timer prescaling when the w atch- dog timer is enabled. the different prescaling values and their corresponding timeout periods are shown in table 10-2 . note: also see figure 29-47 on page 356 . the following code example shows one assemb ly and one c function for turning off the w dt. the example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. table 10-2. w atchdog timer prescale select wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 3.0v typical time-out at v cc = 5.0v 0 0 0 16k cycles 15.4ms 14.7ms 0 0 1 32k cycles 30.8ms 29.3ms 0 1 0 64k cycles 61.6ms 58.7ms 0 1 1 128k cycles 0.12s 0.12s 1 0 0 256k cycles 0.25s 0.23s 1 0 1 512k cycles 0.49s 0.47s 1 1 0 1,024k cycles 1.0s 0.9s 1 1 1 2,048k cycles 2.0s 1.9s 55 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 11. interrupts this section describes the specifics of the interrupt handling as performed in atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p. for a general explanation of the avr interrupt handling, refer to ?reset and interrupt handling? on page 16 . 11.1 interrupt vectors notes: 1. w hen the bootrst fuse is programmed, the device will jump to the boot loader address at reset, see ?boot loader support ? read- w hile- w rite self-programming? on page 266 . table 11-1. reset and interrupt vectors vector no. program address (2) source interrupt definition 1 0x0000 (1) reset external pin, power-on reset, brown-out reset, w atchdog reset, and jtag avr reset 2 0x0002 int0 external interrupt request 0 3 0x0004 pcint0 pin change interrupt request 0 4 0x0006 pcint1 pin change interrupt request 1 5 0x0008 timer2 comp timer/ counter2 compare match 6 0x000a timer2 ovf timer/counter2 overflow 7 0x000c timer1 capt timer/counter1 capture event 8 0x000e timer1 compa timer/counter1 compare match a 9 0x0010 timer1 compb timer/counter1 compare match b 10 0x0012 timer1 ovf timer/counter1 overflow 11 0x0014 timer0 comp timer/ counter0 compare match 12 0x0016 timer0 ovf timer/counter0 overflow 13 0x0018 spi, stc spi serial transfer complete 14 0x001a usart, rx usart0, rx complete 15 0x001c usart, udren usart0 data register empty 16 0x001e usart, tx usart0, tx complete 17 0x0020 usi start usi start condition 18 0x0022 usi overflo w usi overflow 19 0x0024 analog comp analog comparator 20 0x0026 adc adc conversion complete 21 0x0028 ee ready eeprom ready 22 0x002a spm ready store program memory ready 23 0x002c not_used reserved 24 0x002e pcint2 pin change interrupt request 2 25 0x0030 pcint3 pin change interrupt request 3 56 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 2. w hen the ivsel bit in mcucr is set, interrupt ve ctors will be moved to the start of the boot flash section. the address of each interrupt vector will then be the address in this table added to the start address of the boot flash section. table 11-2 on page 56 shows reset and interrupt vectors placement for the various combina- tions of bootrst and ivsel settings. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot sect ion or vice versa. note: 1. the boot reset address is shown in table 25-6 on page 278 . for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. the most typical and general program setup for the reset and interrupt vector addresses in atmega165a/165pa is: address labels code comments 0x0000 jmp reset ; reset handler 0x0002 jmp ext_int0 ; irq0 handler 0x0004 jmp pcint0 ; pcint0 handler 0x0006 jmp pcint1 ; pcint0 handler 0x0008 jmp tim2_comp ; timer2 compare handler 0x000a jmp tim2_ovf ; timer2 overflow handler 0x000c jmp tim1_capt ; timer1 capture handler 0x000e jmp tim1_compa ; timer1 comparea handler 0x0010 jmp tim1_compb ; timer1 compareb handler 0x0012 jmp tim1_ovf ; timer1 overflow handler 0x0014 jmp tim0_comp ; timer0 compare handler 0x0016 jmp tim0_ovf ; timer0 overflow handler 0x0018 jmp spi_stc ; spi transfer complete handler 0x001a jmp usart_rxcn ; usart0 rx complete handler 0x001c jmp usart_dre ; usart0,udrn empty handler 0x001e jmp usart_txcn ; usart0 tx complete handler 0x0020 jmp usi_strt ; usi start condition handler 0x0022 jmp usi_ovfl ; usi overflow handler 0x0024 jmp ana_comp ; analog comparator handler 0x0026 jmp adc ; adc conversion complete handler 0x0028 jmp ee_rdy ; eeprom ready handler 0x002a jmp spm_rdy ; spm ready handler ; 0x002e reset: ldi r16, high(ramend); main program start 0x002f out sph,r16 set stack pointer to top of ram 0x0030 ldi r16, low(ramend) table 11-2. reset and interrupt vectors placement (1) bootrst ivsel reset address interrupt vectors start address 1 0 0x0000 0x0002 1 1 0x0000 boot reset address + 0x0002 0 0 boot reset address 0x0002 0 1 boot reset address boot reset address + 0x0002 57 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 0x0031 out spl,r16 0x0032 sei ; enable interrupts 0x0033 58 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 ; 0x1c2e reset: ldi r16,high(ramend); main program start 0x1c2f out sph,r16 ; set stack pointer to top of ram 0x1c30 ldi r16,low(ramend) 0x1c31 out spl,r16 0x1c32 sei ; enable interrupts 0x1c33 59 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 address labels code comments 0x0000 reset: ldi r16,high(ramend); main program start 0x0001 out sph,r16 ; set stack pointer to top of ram 0x0002 ldi r16,low(ramend) 0x0003 out spl,r16 0x0004 sei ; enable interrupts 0x0005 60 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 11.2 moving interrupts between application and boot space the general interrupt control register controls the placement of the interrupt vector table, see ?mcucr ? mcu control register? on page 61 . to avoid unintentional changes of interrupt vector tables, a special write procedure must be fol- lowed to change the ivsel bit: a. w rite the interrupt vector change enable (ivce) bit to one. b. w ithin four cycles, write the desired value to ivsel while writing a zero to ivce. interrupts will automatically be di sabled while this sequence is executed. interrupts are disabled in the cycle ivce is set, and they remain disabl ed until after the instru ction following the write to ivsel. if ivsel is not written, interrupts remain disabled for four cycles. the i-bit in the status register is unaffected by the automatic disabling. note: if interrupt vectors are placed in the boot loader section and boot lock bit blb02 is programmed, interrupts are disabled while executing from the a pplication section. if interrupt vectors are placed in the application section and boot lock bit blb 12 is programed, interrupts are disabled while executing from the boot loader section. refer to the section ?boot loader support ? read- w hile- w rite self-programming? on page 266 for details on boot lock bits. the following example shows how interrupts are moved. assembly code example move_interrupts: ; get mcucr in r16, mcucr mov r17, r16 ; enable change of interrupt vectors ori r16, (1< 62 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 12. external interrupts the external interrupts are triggered by t he int0 pin or any of the pcint30:0 pins (2) . observe that, if enabled, the interrupts will trigger even if the int0 or pcint30:0 pins are configured as outputs. this feature provides a way of generating a software interrupt. the pin change interrupt pci1 will trigger if any enabled pcint15:8 pin toggles. pin cha nge interrupts pci0 will trigger if any enabled pcint7:0 pin toggles. the pcmsk3 (1) , pcmsk2 (1) , pcmsk1, and pcmsk0 reg- isters control which pins contribute to the pin change interrupts. pin change interrupts on pcint30:0 are detected asynchronously. this implies that these interrupts can be used for wak- ing the part also from sleep modes other than idle mode. the int0 interrupts can be triggered by a falling or rising edge or a low level. this is set up as indicated in the sp ecification for the ?eicra ? external interrupt control register a? on page 64 . w hen the int0 inte rrupt is enabled and is co nfigured as level triggere d, the interrupt will trigger as long as the pin is held low. . note that re cognition of falling or rising edge interrupts on int0 requires the presence of an i/o clock, described in ?clock systems and their distribution? on page 29 . low level interrupt on int0 is detected asynchronously. this implies that this interrupt can be used for waking the part also from sleep modes other than idle mode. the i/o clock is halted in all sleep modes except idle mode. note that if a level triggered interrupt is used for wake-up from power-down, the required level must be held long enough for the mcu to complete the wake-up to trigger the level interrupt. if the level disappears before the end of the start-up ti me, the mcu will still wake up, but no inter- rupt will be generated. the start- up time is defined by the su t and cksel fuses as described in ?system clock and clock options? on page 29 . notes: 1. pcmsk3 and pcmsk2 are only pr esent in atmega3250a/3250pa/6450a/6450p. 2. pcint30:16 are only present in atmega32 50a/3250pa/6450a/6450p. only pcint15:0 are present in atmega165a/165pa; atmega325a/325pa and atmega645a/645p. see ?pin con- figurations? on page 2 and ?register description? on page 64 for details. 12.1 pin change interrupt timing an example of timing of a pin change interrupt is shown in figure 12-1 on page 63 63 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 12-1. pin change interrupt clk pcint(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag pcif pcint(0) pin_sync pcint_syn pin_lat d q le pcint_setflag pcif clk clk pcint(0) in pcm s k(x) pcint_in_(0) 0 x 64 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 12.2 register description 12.2.1 eicra ? external interrupt control register a the external interrupt control register a contains control bits for interrupt sense control. ? bit 1, 0 ? isc01, isc00: interrupt sense control 0 bit 1 and bit 0 the external interrupt 0 is activated by the exte rnal pin int0 if the sreg i-flag and the corre- sponding interrupt mask are set. the level and edges on the external int0 pin that activate the interrupt are defined in table 12-1 . the value on the int0 pin is sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. if low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. 12.2.2 eimsk ? external interrupt mask register ? bit 7 ? pcie3: pin change interrupt enable 3 w hen the pcie3 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 3 is enabled. any change on any enabled pcint30:24 pin will cause an inter- rupt. the corresponding interrupt of pin change interrupt request is executed from the pcint3 interrupt vector. pcint30:24 pins are enabled individually by the pcmsk3 register. note: 1. this bit is a reserved bit in atmega165a/atmega165pa/atmega325a/atmega325pa/atmega645a/atmega645p and should always be written to zero. ? bit 6 ? pcie2: pin change interrupt enable 2 w hen the pcie2 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 2 is enabled. any change on any enabled pcint23:16 pin will cause an inter- rupt. the corresponding interrupt of pin change interrupt request is executed from the pcint2 interrupt vector. pcint23:16 pins are enabled individually by the pcmsk2 register. note: 1. this bit is a reserved bit in atmega165a/atmega165pa/atmega325a/atmega325pa/atmega645a/atmega645p and should always be written to zero. bit 76543210 (0x69) ? ? ? ? ? ? isc01 isc00 eicra read/ w rite rrrrrrr/ w r/ w initial value 0 0 0 0 0 0 0 0 table 12-1. interrupt 0 sense control isc01 isc00 description 0 0 the low level of int0 generates an interrupt request. 0 1 any logical change on int0 generates an interrupt request. 1 0 the falling edge of int0 generates an interrupt request. 1 1 the rising edge of int0 generates an interrupt request. bit 76543210 0x1d (0x3d) pcie3 (1) pcie2 (1) pcie1 pcie0 ? ? ?int0eimsk read/ w rite r r r/ w r/ w rrrr/ w initial value 0 0 0 0 0 0 0 0 65 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 bit 5 ? pcie1: pin change interrupt enable 1 w hen the pcie1 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 1 is enabled. an y change on any enabled pcint 15...8 pin will cause an inter- rupt. the corresponding interrupt of pin change interrupt request is executed from the pci1 interrupt vector. pcint15:8 pins are enabled individually by the pcmsk1 register. ? bit 4 ? pcie0: pin change interrupt enable 0 w hen the pcie0 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 0 is enabled. any change on any enabled pcint7...0 pin will cause an inter- rupt. the corresponding interrupt of pin change interrupt request is executed from the pci0 interrupt vector. pcint7:0 pins are enabled individually by the pcmsk0 register. ? bit 0 ? int0: external interrupt request 0 enable w hen the int0 bit is set (one) and the i-bit in the status register (sreg) is set (one), the exter- nal pin interrupt is enabled. the interrupt sens e control0 bits 1/0 (isc01 and isc00) in the external interrupt control register a (eicra) define whether the external interrupt is activated on rising and/or falling edge of the int0 pin or le vel sensed. activity on the pin will cause an interrupt request even if int0 is configured as an output. the corresponding interrupt of external interrupt request 0 is executed from the int0 interrupt vector. 12.2.3 eifr ? external interrupt flag register ? bit 7 ? pcif3: pin change interrupt flag 3 w hen a logic change on any pcint30:24 pin triggers an interrupt request, pcif3 becomes set (one). if the i-bit in sreg and the pcie3 bit in eimsk are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alter- natively, the flag can be cleared by writing a logical one to it. note: 1. this bit is a reserved bit in atmega165a/atmega165pa/atmega325a/atmega325pa/atmega645a/atmega645p and should always be written to zero. ? bit 6 ? pcif2: pin change interrupt flag 2 w hen a logic change on any pcint24:16 pin triggers an interrupt request, pcif2 becomes set (one). if the i-bit in sreg and the pcie2 bit in eimsk are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alter- natively, the flag can be cleared by writing a logical one to it. note: 1. this bit is a reserved bit in atmega165a/atmega165pa/atmega325a/atmega325pa/atmega645a/atmega645p and should always be written to zero. ? bit 5 ? pcif1: pin change interrupt flag 1 w hen a logic change on any pcint15:8 pin trigge rs an interrupt request, pcif1 becomes set (one). if the i-bit in sreg and the pcie1 bit in eimsk are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alter- natively, the flag can be cleared by writing a logical one to it. bit 76543210 0x1c (0x3c) pcif3 (1) pcif2 (1) pcif1 pcif0 ? ? ? intf0 eifr read/ w rite r/ w r/ w r/ w r/ w rrrr/ w initial value00000000 66 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 ? bit 4 ? pcif0: pin change interrupt flag 0 w hen a logic change on any pcint7:0 pin triggers an interrupt request, pcif0 becomes set (one). if the i-bit in sreg and the pcie0 bit in eimsk are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alter- natively, the flag can be cleared by writing a logical one to it. ? bit 0 ? intf0: external interrupt flag 0 w hen an edge or logic change on the int0 pin triggers an interrupt request, intf0 becomes set (one). if the i-bit in sreg and the int0 bit in eimsk are set (o ne), the mcu will jump to the cor- responding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. this flag is always cleared when int0 is configured as a level interrupt. 12.2.4 pcmsk3 ? pin change mask register 3 (1) note: 1. pcmsk3 and pcmsk2 are only pres ent in atmega3250a/3250pa/6450a/6450p. ? bit 6:0 ? pcint30:24: pin change enable mask 30:24 each pcint30:24-bit selects whether pin change interrupt is enabled on the corresponding i/o pin. if pcint30:24 is set and the pcie3 bit in eimsk is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint30:24 is cleared, pin change interrupt on the corresponding i/o pin is disabled. 12.2.5 pcmsk2 ? pin change mask register 2 (1) note: 1. pcmsk3 and pcmsk2 are only pres ent in atmega3250a/3250pa/6450a/6450p. ? bit 7:0 ? pcint23:16: pin change enable mask 23:16 each pcint23:16 bit selects whether pin change interrupt is enabled on the corresponding i/o pin. if pcint23:16 is set and the pcie2 bit in eimsk is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint23:16 is cleared, pin change interrupt on the corresponding i/o pin is disabled. 12.2.6 pcmsk1 ? pin change mask register 1 ? bit 7:0 ? pcint15:8: pin change enable mask 15:8 each pcint15:8-bit selects whether pin change interrupt is enabled on the corresponding i/o pin. if pcint15:8 is set and the pcie1 bit in eimsk is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint15:8 is cleared, pin change interrupt on the corresponding i/o pin is disabled. bit 76543210 (0x73) ? pcint30 pcint29 pcint28 pcint27 pcint26 pcint25 pcint24 pcmsk3 read/ w rite r r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0x6d) pcint23 pcint22 pcint21 pcint20 pcint19 pcint18 pcint17 pcint16 pcmsk2 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x6c) pcint15 pcint14 pcint13 pcint12 pcint11 pcint10 pcint9 pcint8 pcmsk1 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 67 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 12.2.7 pcmsk0 ? pin change mask register 0 ? bit 7:0 ? pcint7:0: pin change enable mask 7:0 each pcint7:0 bit selects whether pin change interrupt is enabled on the corresponding i/o pin. if pcint7:0 is set and the pcie0 bit in eimsk is set, pin change interrupt is enabled on the cor- responding i/o pin. if pcint7:0 is cleared, pi n change interrupt on the corresponding i/o pin is disabled. bit 76543210 (0x6b) pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 pcmsk0 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 68 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 13. i/o-ports 13.1 overview all avr ports have true read-modify- w rite functionality when used as general digital i/o ports. this means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the sbi and cbi instructions. the same applies when chang- ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). each output buffer has symmetrical drive characteristics with both high sink and source capability. the pin driver is stro ng enough to drive led displays directly. all port pins have indi- vidually selectable pull-up resistors with a suppl y-voltage invariant resistance. all i/o pins have protection diodes to both v cc and ground as indicated in figure 13-1 on page 68 . refer to ?electrical characteristics? on page 317 for a complete list of parameters. if exceeding the pin voltage ?absolute maximum ratings?, resulting currents can harm the device if not limited accordingly. figure 13-1. i/o pin equivalent schematic all registers and bit references in this section are written in general form. a lower case ?x? repre- sents the numbering letter for the port, and a lower case ?n? represents the bit number. however, when using the register or bit defines in a progr am, the precise form must be used. for example, portb3 for bit no. 3 in port b, here documented generally as portxn. the physical i/o regis- ters and bit locations are listed in ?register description? on page 90 . three i/o memory address locations are allocated for each port, one each for the data register ? portx, data direction register ? ddrx, and the port input pins ? pinx. the port input pins i/o location is read only, while the data register and the data direction register are read/write. however, writing a logic one to a bit in the pinx register, will result in a toggle in the correspond- ing bit in the data register. in addition, the pu ll-up disable ? pud bit in mcucr disables the pull-up function for all pins in all ports when set. using the i/o port as general digital i/o is described in ?ports as general digital i/o? on page 69 . most port pins are multiplexed with alternate functions for the peripheral features on the device. how each alternate function interferes with the port pin is described in ?alternate port functions? on page 74 . refer to the individual module sectio ns for a full description of the alter- nate functions. note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital i/o. c pin logic r pu s ee figure "general digital i/o" for details pxn 69 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 13.2 ports as gener al digital i/o the ports are bi-directional i/o ports with optional internal pull-ups. figure 13-2 shows a func- tional description of one i/o-port pin, here generically called pxn. figure 13-2. general digital i/o (1) note: 1. w rx, w px, w dx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. 13.2.1 configuring the pin each port pin consists of three register bits: ddxn, portxn, and pinxn. as shown in ?register description? on page 90 , the ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects the direct ion of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is written logic zero, pxn is configured as an input pin. if portxn is written logic one when the pin is c onfigured as an input pin, the pull-up resistor is activated. to switch the pull-up resistor off, portxn has to be written logic zero or the pin has to be configured as an output pin. the port pins are tri-stated when reset condition becomes active, even if no clocks are running. if portxn is written logic one when the pin is conf igured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). clk rpx rrx rdx wdx pud s ynchronizer wdx: write ddrx wrx: write portx rrx: read portx regi s ter rpx: read portx pin pud: pullup di s able clk i/o : i/o clock rdx: read ddrx d l q q re s et re s et q q d q q d clr portxn q q d clr ddxn pinxn data b u s s leep s leep: s leep control pxn i/o wpx 0 1 wrx wpx: write pinx regi s ter 70 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 13.2.2 toggling the pin w riting a logic one to pinxn toggles the value of portxn, independent on the value of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. 13.2.3 switching between input and output w hen switching between tri-state ({ddxn, portxn} = 0b00) and output high ({ddxn, portxn} = 0b11), an intermediate state with either pull-up enabled {ddxn, portxn} = 0b01) or output low ({ddxn, portxn} = 0b10) must occur. norma lly, the pull-up enabled state is fully accept- able, as a high-impedant enviro nment will not notice the differenc e between a strong high driver and a pull-up. if this is not the case, the pud bit in the mcucr register can be set to disable all pull-ups in all ports. switching between input with pull-up and output low generates the same problem. the user must use either the tri-state ({ddxn, portxn} = 0b00) or the output high state ({ddxn, portxn} = 0b11) as an intermediate step. table 13-1 on page 70 summarizes the control signals for the pin value. 13.2.4 reading the pin value independent of the setting of data direction bit ddxn, the port pin can be read through the pinxn register bit. as shown in figure 13-2 , the pinxn register bit and the preceding latch con- stitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. figure 13-3 shows a timing dia- gram of the synchronization when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. table 13-1. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low. 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) 71 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 13-3. synchronization when reading an externally applied pin value consider the clock period starting shortly after the first falling edge of the system cl ock. the latch is closed when the clock is low, and goes transpa rent when the clock is high, as indicated by the shaded region of the ?sync latch? signal. the signal value is latched when the system clock goes low. it is clocked into the pinxn register at the succeeding positive clock edge. as indi- cated by the two arrows tpd,max and tpd,min, a single signal tr ansition on the pin will be delayed between ? and 1? system clock period depending upon the time of assertion. w hen reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in figure 13-4 . the out instruction sets the ?sync latch? signal at the positive edge of the clock. in this case, the delay tpd through the synchronizer is 1 system clock period. figure 13-4. synchronization when reading a software assigned pin value the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. the resulting pin xxx in r17, pinx 0x00 0xff in s truction s s ync latch pinxn r17 xxx s y s tem clk t pd, max t pd, min out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 72 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 values are read back again, but as previously di scussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. note: 1. for the assembly program, two temporary registers are used to minimize the time from pull- ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. 13.2.5 digital input enable and sleep modes as shown in figure 13-2 , the digital input signal can be clamped to ground at the input of the schmidt trigger. the signal denot ed sleep in the figure, is set by the mcu sleep controller in power-down mode, power-save mode, and standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to v cc /2. sleep is overridden for port pins enabled as ex ternal interrupt pins. if the external interrupt request is not e nabled, sleep is active also for these pins. sl eep is also overri dden by various other alternate functions as described in ?alternate port functions? on page 74 . if a logic high level (?one?) is present on an asynchronous external interrupt pin configured as ?interrupt on rising edge, falling edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the above mentioned sleep mode, as the clamping in these sleep mode produces the requested logic change. assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< 74 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 13.3 alternate port functions most port pins have alternate functions in addition to being general digital i/os. figure 13-5 shows how the port pin control signals from the simplified figure 13-2 can be overridden by alternate functions. the overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the avr microcontroller family. figure 13-5. alternate port functions (1) note: 1. w rx, w px, w dx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. all other signals are unique for each pin. table 13-2 on page 75 summarizes the function of the overriding signals. the pin and port indexes from figure 13-5 on page 74 are not shown in the succeeding tables. the overriding signals are generated internally in the modules having the alternate function. clk rpx rrx wrx rdx wdx pud s ynchronizer wdx: write ddrx wrx: write portx rrx: read portx regi s ter rpx: read portx pin pud: pullup di s able clk i/o : i/o clock rdx: read ddrx d l q q s et clr 0 1 0 1 0 1 dixn aioxn dieoexn pvovxn pvoexn ddovxn ddoexn puoexn puovxn puoexn: pxn pull-up override enable puovxn: pxn pull-up override value ddoexn: pxn data direction override enable ddovxn: pxn data direction override value pvoexn: pxn port value override enable pvovxn: pxn port value override value dixn: digital input pin n on portx aioxn: analog input/output pin n on portx re s et re s et q q d clr q q d clr q q d clr pinxn portxn ddxn data b u s 0 1 dieovxn s leep dieoexn: pxn digital input-enable override enable dieovxn: pxn digital input-enable override value s leep: s leep control pxn i/o 0 1 ptoexn wpx ptoexn: pxn, port toggle override enable wpx: write pinx 75 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 the following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. refer to the alternate function description for further details. table 13-2. generic description of overriding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardless of the setting of the ddxn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabled when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital i nput enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regardless of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alternate functions. in the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to/from alternate functions. the signal is connected directly to the pad, and can be used bi- directionally. 76 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 13.3.1 alternate functions of port b the port b pins with alternate functions are shown in table 13-3 . the alternate pin configuration is as follows: ?oc2a/pcint15 , bit 7 oc2, output compare match a output: the pb7 pin can serve as an external output for the timer/counter2 output compare a. the pin has to be configured as an output (ddb7 set (one)) to serve this function. the oc2a pin is also the output pin for the p w m mode timer function. pcint15, pin change interrupt source 15: the pb7 pin can serve as an external interrupt source. ?oc1b/pcint14 , bit 6 oc1b, output compare match b output: the pb6 pin can serve as an external output for the timer/counter1 output compare b. the pin has to be configured as an output (ddb6 set (one)) to serve this function. the oc1b pin is also the output pin for the p w m mode timer function. pcint14, pin change interrupt source 14: the pb6 pin can serve as an external interrupt source. ?oc1a/pcint13 , bit 5 oc1a, output compare match a output: the pb5 pin can serve as an external output for the timer/counter1 output compare a. the pin has to be configured as an output (ddb5 set (one)) to serve this function. the oc1a pin is also the output pin for the p w m mode timer function. pcint13, pin change interrupt source 13: the pb5 pin can serve as an external interrupt source. ?oc0a/pcint12 , bit 4 oc0a, output compare match a output: the pb4 pin can serve as an external output for the timer/counter0 output compare a. the pin has to be configured as an output (ddb4 set (one)) to serve this function. the oc0a pin is also the output pin for the p w m mode timer function. pcint12, pin change interrupt source 12: the pb4 pin can serve as an external interrupt source. table 13-3. port b pins alternate functions port pin alternate functions pb7 oc2a/pcint15 (output compare and p w m output a for timer/counter2 or pin change interrupt15). pb6 oc1b/pcint 14 (output compare and p w m output b for timer/counter1 or pin change interrupt14). pb5 oc1a/pcint13 (output compare and p w m output a for timer/counter1 or pin change interrupt13). pb4 oc0a/pcint12 (output compare and p w m output a for timer/counter0 or pin change interrupt12). pb3 miso/pcint11 (spi bus master input/slave output or pin change interrupt11). pb2 mosi/pcint10 (spi bus master output/slave i nput or pin change interrupt10). pb1 sck/pcint9 (spi bus serial clock or pin change interrupt9). pb0 ss/pcint8 (spi slave select input or pin change interrupt8). 77 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 ? miso/pcint11 ? port b, bit 3 miso: master data input, slave data output pin for spi. w hen the spi is enabled as a master, this pin is configured as an input regardless of the setting of ddb3. w hen the spi is enabled as a slave, the data direction of th is pin is controlled by ddb3. w hen the pin is forced to be an input, the pull-up can still be controlled by the portb3 bit. pcint11, pin change interrupt source 11: the pb3 pin can serve as an external interrupt source. ? mosi/pcint10 ? port b, bit 2 mosi: spi master data output, slave data input for spi. w hen the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb2. w hen the spi is enabled as a master, the data direction of this pin is controlled by ddb2. w hen the pin is forced to be an input, the pull-up can still be controlled by the portb2 bit. pcint10, pin change interrupt source 10: the pb2 pin can serve as an external interrupt source. ? sck/pcint9 ? port b, bit 1 sck: master clock output, slave clock input pin for spi. w hen the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb1. w hen the spi is enabled as a master, the data direction of this pin is controlled by ddb1. w hen the pin is forced to be an input, the pull-up can still be controlled by the portb1 bit. pcint9, pin change interrupt source 9: the pb1 pin can serve as an external interrupt source. ?ss /pcint8 ? port b, bit 0 ss : slave port select input. w hen the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb0. as a slave, the spi is activated when this pin is driven low. w hen the spi is enabled as a master, the data direct ion of this pin is controlled by ddb0. w hen the pin is forced to be an input, the pu ll-up can still be controlled by the portb0 bit pcint8, pin change interrupt source 8: the pb0 pin can serve as an external interrupt source. table 13-4 and table 13-5 relate the alternate functions of port b to the overriding signals shown in figure 13-5 on page 74 . spi mstr input and spi sl ave output constitute the miso signal, while mosi is divided into spi mstr output and spi slave input. 78 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 table 13-4. overriding signals for alternate functions in pb7:pb4 signal name pb7/oc2a/ pcint15 pb6/oc1b/ pcint14 pb5/oc1a/ pcint13 pb4/oc0a/ pcint12 puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe oc2a enable oc1b enable oc1a enable oc0a enable pvov oc2a oc1b oc1a oc0a ptoe ? ? ? ? dieoe pcint15 ? pcie1 pcint14 ? pcie 1 pcint13 ? pcie1 pcint12 ? pcie1 dieov 1 1 1 1 di pcint15 input pcint14 input pcint13 input pcint12 input aio ? ? ? ? table 13-5. overriding signals for alternate functions in pb3:pb0 signal name pb3/miso/ pcint11 pb2/mosi/ pcint10 pb1/sck/ pcint9 pb0/ss / pcint8 puoe spe ? mstr spe ? mstr spe ? mstr spe ? mstr puov portb3 ? pud portb2 ? pud portb1 ? pud portb0 ? pud ddoe spe ? mstr spe ? mstr spe ? mstr spe ? mstr ddov 0 0 0 0 pvoe spe ? mstr spe ? mstr spe ? mstr 0 pvov spi slave output spi mstr output sck output 0 ptoe ? ? ? ? dieoe pcint11 ? pcie1 pcint10 ? pc ie1 pcint9 ? pcie1 pcint8 ? pcie1 dieov 1 1 1 1 di pcint11 input spi mstr input pcint10 input spi slave input pcint9 input sck input pcint8 input spi ss aio ? ? ? ? 79 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 13.3.2 alternate functions of port d the port d pins with alternate functions are shown in table 13-6 . the alternate pin configuration is as follows: ?int0 ? port d, bit 1 int0, external interrupt source 0. the pd1 pin can serve as an external interrupt source to the mcu. ? icp1 ? port d, bit 0 icp1 ? input capture pin1: the pd0 pin can act as an input capture pin for timer/counter1. table 13-7 relates the alternate functions of port d to the overriding signals shown in figure 13- 5 on page 74 . table 13-6. port d pins alternate functions port pin alternate function pd7 ? pd6 ? pd5 ? pd4 ? pd3 ? pd2 ? pd1 int0 (external interrupt0 input) pd0 icp1 (timer/counter1 input capture pin) table 13-7. overriding signals for alte rnate functions in pd1:pd0 signal name pd1/int0 pd0/icp1 puoe 0 0 puov 0 0 ddoe 0 0 ddov 0 0 pvoe 0 0 pvov 0 0 ptoe ? ? dieoe int0 enable 0 dieov int0 enable 0 di int0 input icp1 input aio ? ? 80 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 13.3.3 alternate functions of port e the port e pins with alternate functions are shown in table 13-8 . ? pcint7 ? port e, bit 7 pcint7, pin change interrupt source 7: the pe7 pin can serve as an external interrupt source. clko, divided system clock: the divided syst em clock can be output on the pe7 pin. the divided system clock will be output if the ck out fuse is programmed, regardless of the porte7 and dde7 settings. it will also be output during reset. ? do/pcint6 ? port e, bit 6 do, universal serial interface data output. pcint6, pin change interrupt source 6: the pe6 pin can serve as an external interrupt source. ? di/sda/pcint5 ? port e, bit 5 di, universal serial interface data input. sda, two-wire serial interface data: pcint5, pin change interrupt source 5: the pe5 pin can serve as an external interrupt source. ? usck/scl/pcint4 ? port e, bit 4 usck, universal serial interface clock. scl, two-wire serial interface clock. pcint4, pin change interrupt source 4: the pe4 pin can serve as an external interrupt source. ? ain1/pcint3 ? port e, bit 3 ain1 ? analog comparator negative input. this pi n is directly connected to the negative input of the analog comparator. pcint3, pin change interrupt source 3: the pe3 pin can serve as an external interrupt source. table 13-8. port e pins alternate functions port pin alternate function pe7 pcint7 (pin change interrupt7) clko (divided system clock) pe6 do/pcint6 (usi data output or pin change interrupt6) pe5 di/sda/pcint5 (usi data input or t w i serial data or pin change interrupt5) pe4 usck/scl/pcint4 (usart external clock input/output or t w i serial clock or pin change interrupt4) pe3 ain1/pcint3 (analog comparator nega tive input or pin change interrupt3) pe2 xck/ain0/ pcint2 (usart extern al clock or analog comparator positive input or pin change interrupt2) pe1 txd/pcint1 (usart transmit pin or pin change interrupt1) pe0 rxd/pcint0 (usart receive pin or pin change interrupt0) 81 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 ? xck/ain0/pcint2 ? port e, bit 2 xck, usart external clock. the data direction re gister (dde2) controls whether the clock is output (dde2 set) or input (dde2 cleared). t he xck pin is active only when the usart oper- ates in synchronous mode. ain0 ? analog comparator positive input. this pin is directly connected to the positive input of the analog comparator. pcint2, pin change interrupt source 2: the pe2 pin can serve as an external interrupt source. ? txd/pcint1 ? port e, bit 1 txd0, uart0 transmit pin. pcint1, pin change interrupt source 1: the pe1 pin can serve as an external interrupt source. ? rxd/pcint0 ? port e, bit 0 rxd, usart receive pin. receive da ta (data input pin for the usart). w hen the usart receiver is enabled this pin is configured as an input regardless of the value of dde0. w hen the usart forces this pin to be an input, a logical one in porte0 will turn on the internal pull-up. pcint0, pin change interrupt source 0: the pe0 pin can serve as an external interrupt source. table 13-9 and table 13-10 relates the alternate functions of port e to the overriding signals shown in figure 13-5 on page 74 . note: 1. ckout is one if the ckout fuse is programmed table 13-9. overriding signals for alternate functions pe7:pe4 signal name pe7/pcint7 pe6/do/ pcint6 pe5/di/sda/ pcint5 pe4/usck/scl/ pcint4 puoe 0 0 usi_t w o- w ire usi_t w o- w ire puov 0 0 0 0 ddoe ckout (1) 0usi_t w o- w ire usi_t w o- w ire ddov 1 0 (sda + porte5 ) ? dde5 (usi_scl_hold ? porte4 ) + dde4 pvoe ckout (1) usi_three- w ire usi_t w o- w ire ? dde5 usi_t w o- w ire ? dde4 pvov clk i/o do 0 0 ptoe ? ? 0 usitc dieoe pcint7 ? pcie 0 pcint6 ? pcie0 (pcint5 ? pcie0) + usisie (pcint4 ? pcie0) + usisie dieov 1 1 1 1 di pcint7 input pcint6 input di/sda input pcint5 input usckl/scl input pcint4 input aio ? ? ? ? 82 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 note: 1. ain0d and ain1d is described in ?didr1 ? digital input disable register 1? on page 213 . 13.3.4 alternate functions of port f the port f has an alternate function as analog input for the adc as shown in table 13-11 . if some port f pins are configured as outputs, it is essential that these do not switch when a con- version is in progress. this might corrupt the re sult of the conversion. if the jtag interface is enabled, the pull-up re sistors on pins pf7(tdi), pf5(tms) and pf4(tck) will be activated even if a reset occurs. ? tdi, adc7 ? port f, bit 7 adc7, analog to digital converter, channel 7 . tdi, jtag test data in: serial input data to be shifted in to the instruction register or data reg- ister (scan chains). w hen the jtag interface is enabled, th is pin can not be used as an i/o pin. table 13-10. overriding signals for alternate functions in pe3:pe0 signal name pe3/ain1/ pcint3 pe2/xck/ain0/ pcint2 pe1/txd/ pcint1 pe0/rxd/pcint0 puoe 0 0 txenn rxenn puov 0 0 0 porte0 ? pud ddoe 0 0 txenn rxenn ddov 0 0 1 0 pvoe 0 xck output enable txenn 0 pvov 0 xck txd 0 ptoe ? ? ? ? dieoe (pcint3 ? pcie0) + ain1d (1) (pcint2 ? pcie0) + ain0d (1) pcint1 ? pcie0 pcint0 ? pcie0 dieov pcint3 ? pcie0 pcint2 ? pcie0 1 1 di pcint3 input xck/pcint2 input pcint1 input rxd/pcint0 input aio ain1 input ain0 input ? ? table 13-11. port f pins alternate functions port pin alternate function pf7 adc7/tdi (adc input channel 7 or jtag test data input) pf6 adc6/tdo (adc input channel 6 or jtag test data output) pf5 adc5/tms (adc input channel 5 or jtag test mode select) pf4 adc4/tck (adc input channel 4 or jtag test clock) pf3 adc3 (adc input channel 3) pf2 adc2 (adc input channel 2) pf1 adc1 (adc input channel 1) pf0 adc0 (adc input channel 0) 83 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 ? tdo, adc6 ? port f, bit 6 adc6, analog to digital converter, channel 6 . tdo, jtag test data out: serial output data from instruction register or data register. w hen the jtag interface is enabled, this pin can not be used as an i/o pin. in tap states that shift out data, the tdo pin drives actively. in other states the pin is pulled high. ? tms, adc5 ? port f, bit 5 adc5, analog to digital converter, channel 5 . tms, jtag test mode select: this pin is used fo r navigating through the tap-controller state machine. w hen the jtag interface is enabled, this pin can not be used as an i/o pin. ? tck, adc4 ? port f, bit 4 adc4, analog to digital converter, channel 4 . tck, jtag test clock: jtag oper ation is synchronous to tck. w hen the jtag interface is enabled, this pin can not be used as an i/o pin. ? adc3 - adc0 ? port f, bit 3:0 analog to digital converter, channel 3-0. table 13-12. overriding signals for alternate functions in pf7:pf4 signal name pf7/adc7/tdi pf6/adc6/t do pf5/adc5/tms pf4/4/tck puoe jtagen jtagen jtagen jtagen puov 1 1 1 1 d d o e j tag e n j tag e n j tag e n j tag e n ddov 0 shift_ir + shift_dr 0 0 pvoe 0 jtagen 0 0 pvov 0 tdo 0 0 ptoe ? ? ? ? d i e o e j tag e n j tag e n j tag e n j tag e n dieov 0 0 0 1 di ? ? ? ? aio tdi adc7 input adc6 input tms adc5 input tck adc4 input 84 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 13.3.5 alternate functions of port g the alternate pin configuration is as follows: note: 1. port g, pg5 is input only. pull-up is always on. see table 26-3 on page 284 for rstdisbl fuse. the alternate pin configuration is as follows: ? reset ? port g, bit 5 reset : external reset input. w hen the rstdisbl fuse is pr ogrammed (?0?), pg5 will function as input with pu ll-up always on. ? t0 ? port g, bit 4 t0, timer/counter0 counter source. ? t1 ? port g, bit 3 t1, timer/counter1 counter source. table 13-13. overriding signals for alternate functions in pf3:pf0 signal name pf3/adc3 pf2/ adc2 pf1/adc1 pf0/adc0 puoe0000 puov0000 ddoe0000 ddov0000 pvoe0000 pvov0000 ptoe???? dieoe0000 dieov0000 di???? aio adc3 input adc2 input adc1 input adc0 input table 13-14. port g pins alternate functions (1) port pin alternate function pg5 reset pg4 t0 (timer/counter0 clock input) pg3 t1 (timer/counter1 clock input) pg2 ? pg1 ? pg0 ? 85 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 table 13-14 and table 13-15 relates the alternate functions of port g to the overriding signals shown in figure 13-5 on page 74 . 13.3.6 alternate functions of port h port h is only present in atmega3250a/3250p a/6450a/6450p. the alternate pin configuration is as follows: the alternate pin configuration is as follows: ? pcint23 ? port h, bit 7 pcint23, pin change interrupt source 23: the ph7 pin can serve as an external interrupt source. ? pcint22 ? port h, bit 6 pcint22, pin change interrupt source 22: the ph6 pin can serve as an external interrupt source. table 13-15. overriding signals for alternate functions in pg4:pg3 signal name pg4/t0 pg3/t1/ puoe 0 0 puov 0 0 ddoe 0 0 ddov 1 1 pvoe 0 0 pvov 0 0 ptoe ? ? dieoe 0 0 dieov 0 0 di t0 input t1 input aio ? ? table 13-16. port h pins alternate functions port pin alternate function ph7 pcint23(pin change interrupt23) ph6 pcint22 (pin change interrupt22) ph5 pcint21(pin change interrupt21) ph4 pcint20(pin change interrupt20) ph3 pcint19 (pin change interrupt19) ph2 pcint18(pin change interrupt18) ph1 pcint17(pin change interrupt17) ph0 pcint16(pin change interrupt16) 86 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 ? pcint21 ? port h, bit 5 pcint21, pin change interrupt source 21: the ph5 pin can serve as an external interrupt source. ? pcint20 ? port h, bit 4 pcint20, pin change interrupt source 20: the ph4 pin can serve as an external interrupt source. ? pcint19? port h, bit 3 pcint19, pin change interrupt source 19: the ph3 pin can serve as an external interrupt source. ? pcint18 ? port h, bit 2 pcint18, pin change interrupt source 18: the ph2 pin can serve as an external interrupt source. ? pcint17/seg ? port h, bit 1 pcint17, pin change interrupt source 17: the p1 pin can serve as an external interrupt source. ? pcint16 ? port h, bit 0 pcint16, pin change interrupt source 16: the ph0 pin can serve as an external interrupt source. table 13-17 and table 13-18 relates the alternate functions of port h to the overriding signals shown in figure 13-5 on page 74 . table 13-17. overriding signals for alte rnate functions in ph7:ph4 signal name ph7/pcint23 ph6/p cint22 ph5/pcint21 ph4/pcint20 puoe0000 puov0000 ddoe0000 ddov0000 pvoe0000 pvov0000 ptoe???? dieoe pcint23 ? pcie0 pcint22 ? pcie 0 pcint21 ? pcie0 pcint20 ? pcie0 dieov0000 di pcint23 input pcint22 input pcint21 input pcint20 input aio???? 87 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 13.3.7 alternate functions of port j port j is only present in atmega3250a/3250pa/6450a/6450p. the alternate pin configuration is as follows: the alternate pin configuration is as follows: ? pcint30 ? port j, bit 6 pcint30, pin change interrupt source 30: the pe30 pin can serve as an external interrupt source. ? pcint29 ? port j, bit 5 pcint29, pin change interrupt source 29: the pe29 pin can serve as an external interrupt source. ? pcint28 ? port j, bit 4 pcint28, pin change interrupt source 28: the pe28 pin can serve as an external interrupt source. table 13-18. overriding signals for alte rnate functions in ph3:ph0 signal name ph3/pcint19 ph2/p cint18 ph1/pcint17 ph0/pcint16 puoe0000 puov0000 ddoe0000 ddov0000 pvoe0000 pvov0000 ptoe???? dieoe pcint19 ? pcie0 pcint18 ? pcie 0 pcint17 ? pcie0 pcint16 ? pcie0 dieov0000 di pcint19 input pcint18 input pcint17 input pcint16 input aio???? table 13-19. port j pins alternate functions port pin alternate function pj6 pcint30(pin change interrupt30) pj5 pcint29(pin change interrupt29) pj4 pcint28(pin change interrupt28) pj3 pcint27(pin change interrupt27) pj2 pcint26(pin change interrupt26) pj1 pcint25(pin change interrupt25) pj0 pcint24(pin change interrupt26) 88 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 ? pcint27 ? port j, bit 3 pcint27, pin change interrupt source 27: the pe27 pin can serve as an external interrupt source. ? pcint26 ? port j, bit 2 pcint26, pin change interrupt source 26: the pe26 pin can serve as an external interrupt source. ? pcint25 ? port j, bit 1 pcint25, pin change interrupt source 25: the pe25 pin can serve as an external interrupt source. ? pcint24 ? port j, bit 0 pcint24, pin change interrupt source 24: the pe24 pin can serve as an external interrupt source. table 13-20 and table 13-21 relates the alternate functions of port j to the overriding signals shown in figure 13-5 on page 74 . table 13-20. overriding signals for alternate functions in pj7:pj4 signal name pj7 pj6/pcint3 0 pj5/pcint29 pj4/pcint28 puoe0000 puov0000 ddoe0000 ddov0000 pvoe0000 pvov0000 ptoe???? dieoe 0 pcint30 ? pcie0 pcint29 ? pcie0 pcint28 ? pcie0 dieov0000 di???? aio???? 89 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 table 13-21. overriding signals for alternate functions in pj3:pj0 signal name pj3/pcint27 pj2/p cint26 pj1/pcint25 pj0/pcint24 puoe0000 puov0000 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe0000 pvov0000 ptoe???? dieoe pcint27 ? pcie0 pcint26 ? pc ie0 pcint25 ? pcie0 pcint24 ? pcie0 dieov0000 di???? aio???? 90 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 13.4 register description 13.4.1 mcucr ? mcu control register ? bit 4 ? pud: pull-up disable w hen this bit is written to one, the pull-ups in the i/o ports are disabled even if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0b01). see ?con- figuring the pin? on page 69 for more details about this feature. 13.4.2 porta ? port a data register 13.4.3 ddra ? port a data direction register 13.4.4 pina ? port a input pins address 13.4.5 portb ? port b data register 13.4.6 ddrb ? port b data direction register 13.4.7 pinb ? port b input pins address bit 7 6 5 4 3 2 1 0 0x35 (0x55) jtd bods bodse pud ? ? ivsel ivce mcucr read/ w rite r/ w rrr/ w rrr/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x02 (0x22) porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 porta read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x01 (0x21) dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x00 (0x20) pina7 pina6 pina5 pina4 pi na3 pina2 pina1 pina0 pina read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 0x05 (0x25) portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 portb read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x04 (0x24) ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x03 (0x23) pinb7 pinb6 pinb5 pinb4 pi nb3 pinb2 pinb1 pinb0 pinb read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value n/a n/a n/a n/a n/a n/a n/a n/a 91 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 13.4.8 portc ? port c data register 13.4.9 ddrc ? port c data direction register 13.4.10 pinc ? port c input pins address 13.4.11 portd ? port d data register 13.4.12 ddrd ? port d data direction register 13.4.13 pind ? port d input pins address 13.4.14 porte ? port e data register 13.4.15 ddre ? port e data direction register bit 76543210 0x08 (0x28) portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 portc read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x07 (0x27) ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x06 (0x26) pinc7 pinc6 pinc5 pinc4 pi nc3 pinc2 pinc1 pinc0 pinc read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 0x0b (0x2b) portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 portd read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x0a (0x2a) ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x09 (0x29) pind7 pind6 pind5 pind4 pi nd3 pind2 pind1 pind0 pind read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 0x0e (0x2e) porte7 porte6 porte5 porte4 porte3 porte2 porte1 porte0 porte read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x0d (0x2d) dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 ddre read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 92 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 13.4.16 pine ? port e input pins address 13.4.17 portf ? port f data register 13.4.18 ddrf ? port f data direction register 13.4.19 pinf ? port f input pins address 13.4.20 portg ? port g data register 13.4.21 ddrg ? port g data direction register 13.4.22 ping ? port g input pins address 13.4.23 porth ? port h data register (1) bit 76543210 0x0c (0x2c) pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 pine read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 0x11 (0x31) portf7 portf6 portf5 portf4 portf3 portf2 portf1 portf0 portf read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x10 (0x30) ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 ddrf read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x0f (0x2f) pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 pinf read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 0x14 (0x34) ? ? portg4 portg4 portg3 portg2 portg1 portg0 portg read/ w riterrrr/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x13 (0x33) ? ? ddg5 ddg4 ddg3 ddg2 ddg1 ddg0 ddrg read/ w riterrrr/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 0x12 (0x32) ? ? ping5 ping4 ping3 ping2 ping1 ping0 ping read/ w rite r r r r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 n/a n/a n/a n/a n/a bit 7 6543210 (0xda) porth7 porth6 porth5 porth4 porth3 porth2 porth1 porth0 porth read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 93 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 13.4.24 ddrh ? port h data direction register (1) 13.4.25 pinh ? port h input pins address (1) 13.4.26 portj ? port j data register (1) 13.4.27 ddrj ? port j data direction register (1) 13.4.28 pinj ? port j input pins address (1) note: 1. register only available in atmega3250a/3250pa/6450a/6450p. bit 76543210 (0xd9) ddh7 ddh6 ddh5 ddh4 ddh3 ddh2 ddh1 ddh0 ddrh read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0xd8) pinh7 pinh6 pinh5 pinh4 pinh3 pinh2 pinh1 pinh0 pinh read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 (0xdd) ? portj6 portj5 portj4 portj3 portj2 portj1 portj0 portj read/ w rite r r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0xdc) ? ddj6 ddj5 ddj4 ddj3 ddj2 ddj1 ddj0 ddrj read/ w rite r r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0xdb) ? pinj6 pinj5 pinj4 pinj3 pinj2 pinj1 pinj0 pinj read/ w rite r r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 n/a n/a n/a n/a n/a n/a n/a 94 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 14. 8-bit timer/counter0 with pwm 14.1 features ? single compare unit counter ? clear timer on compare match (auto reload) ? glitch-free, phase correct pu lse width modulator (pwm) ? frequency generator ? external event counter ? 10-bit clock prescaler ? overflow and compare match inte rrupt sources (tov0 and ocf0a) 14.2 overview timer/counter0 is a general purpose, single compare unit, 8-bit timer/counter module. a simpli- fied block diagram is shown in figure 14-1 . for the actual placement of i/o pins, refer to ?pin configurations? on page 2 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit locations are listed in the ?register description? on page 105 . figure 14-1. 8-bit timer/counter block diagram 14.2.1 definitions many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 0. a lower case ?x? replaces the output com- pare unit number, in this case unit a. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt0 for accessing timer/counter0 counter value and so on. timer/counter data b u s = tcntn waveform generation ocn = 0 control logic = 0xff bottom count clear direction tovn (int.req.) ocrn tccrn clock s elect tn edge detector ( from prescaler ) clk tn top ocn (int.req.) 95 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 the definitions in table 14-1 are also used extensively throughout the document. 14.2.2 registers the timer/counter (tcnt0) and output compare register (ocr0a) are 8-bit registers. inter- rupt request (abbreviated to int.req. in the figure) signals are all visible in the timer interrupt flag register (tifr0). all interrupts are individually masked with the timer interrupt mask reg- ister (timsk0). tifr0 and timsk0 are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the t0 pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t0 ). the double buffered output compare register (ocr0a) is compared with the timer/counter value at all times. the result of the compare can be used by the w aveform generator to gener- ate a p w m or variable frequency output on the output compare pin (oc0a). see ?output compare unit? on page 96. for details. the compare match ev ent will also set the compare flag (ocf0a) which can be used to generate an output compare interrupt request. 14.3 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs02:0) bits located in the timer/counter control register (tccr0a). for details on clock sources and pres- caler, see ?timer/counter0 and timer/counter1 prescalers? on page 137 . 14.4 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 14-2 shows a block diagram of the counter and its surroundings. figure 14-2. counter unit block diagram table 14-1. timer/counter definitions bottom the counter reaches the bottom when it becomes 0x00. max the counter reaches its maximum wh en it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. the assignment is dependent on the mode of operation. data b u s tcntn control logic count tovn (int.req.) clock s elect top tn edge detector ( from prescaler ) clk tn bottom direction clear 96 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 signal description (internal signals): count increment or decrement tcnt0 by 1. direction select between increment and decrement. clear clear tcnt0 (set all bits to zero). clk t n timer/counter clock, referred to as clk t0 in the following. top signalize that tcnt0 has reached maximum value. bottom signalize that tcnt0 has re ached minimum value (zero). depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t0 ). clk t0 can be generated from an external or internal clock source, selected by the clock select bits (cs02:0). w hen no clock source is selected (cs02:0 = 0) the timer is stopped. however, the tcnt0 value can be accessed by the cpu, regardless of whether clk t0 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the w gm01 and w gm00 bits located in the timer/counter control register (tccr0a). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare output oc0a. for more details about advanced count ing sequences and waveform generation, see ?modes of operation? on page 99 . the timer/counter overflow flag (tov0) is set according to the mode of operation selected by the w gm01:0 bits. tov0 can be used for generating a cpu interrupt. 14.5 output compare unit the 8-bit comparator continuously compares tcnt0 with the output compare register (ocr0a). w henever tcnt0 equals ocr0a, the comparator signals a match. a match will set the output compare flag (ocf0a) at the next timer clock cycle. if enabled (ocie0a = 1 and global interrupt flag in sreg is set), the output compare flag generates an output compare interrupt. the ocf0a flag is automatically cleared when the interrupt is executed. alternatively, the ocf0a flag can be cleared by software by writ ing a logical one to its i/o bit location. the w aveform generator uses the match signal to generate an output according to operating mode set by the w gm01:0 bits and compare output mode (com0a1:0) bits. the max and bottom sig- nals are used by the w aveform generator for handling the special cases of the extreme values in some modes of operation ( see ?modes of operation? on page 99. ). figure 14-3 shows a block diagram of the output compare unit. 97 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 14-3. output compare unit, block diagram the ocr0a register is double buffered when using any of the pulse w idth modulation (p w m) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buff- ering is disabled. the double buffering synchron izes the update of the ocr0 compare register to either top or bottom of the counting sequenc e. the synchronization prevents the occurrence of odd-length, non-symmetrical p w m pulses, thereby making the output glitch-free. the ocr0a register access may seem complex, but this is not case. w hen the double buffer- ing is enabled, the cpu has access to the ocr0 a buffer register, and if double buffering is disabled the cpu will access the ocr0a directly. 14.5.1 force output compare in non-p w m waveform generation modes, the match output of the comparator can be forced by writing a one to the fo rce output compare (foc0a) bit. fo rcing compare match will not set the ocf0a flag or reload/clear the ti mer, but the oc0a pin will be updated as if a real compare match had occurred (the com0a1:0 bits settings define whether the oc0a pin is set, cleared or toggled). 14.5.2 compare match bloc king by tcnt0 write all cpu write operations to th e tcnt0 register will block any co mpare match that occur in the next timer clock cycle, even when the timer is stopped. this feature allo ws ocr0a to be initial- ized to the same value as tcnt0 without triggering an interrupt when the timer/counter clock is enabled. 14.5.3 using the output compare unit since writing tcnt0 in any mode of operation will block all comp are matches for one timer clock cycle, there are risks involved when changing tcnt0 when using the output compare unit, independently of whether the timer/counter is running or not. if the value written to tcnt0 equals the ocr0a value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write the tcnt0 value equal to bottom when the counter is down counting. ocfn x (int.req.) = ( 8 -bit comparator ) ocrnx ocnx data b u s tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 98 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 the setup of the oc0a should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc0a value is to use the force output com- pare (foc0a) strobe bits in normal mode. the oc0a register keeps its value even when changing between w aveform generation modes. be aware that the com0a1:0 bits are not double buffered together with the compare value. changing the com0a1:0 bits will take effect immediately. 14.6 compare match output unit the compare output mode (com0a1:0) bits have two functions. the w aveform generator uses the com0a1:0 bits for defining the output compare (oc0a) state at the next compare match. also, the com0a1:0 bits control the oc0a pin output source. figure 14-4 shows a sim- plified schematic of the logic affected by the com0a1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control regis- ters (ddr and port) that are affected by the com0a1:0 bits are shown. w hen referring to the oc0a state, the reference is for the internal oc0a register, not the oc0a pin. if a system reset occur, the oc0a register is reset to ?0?. figure 14-4. compare match output unit, schematic the general i/o port function is overridden by the output compare (oc0a) from the w aveform generator if either of the com0a1:0 bits are set. however, the oc0a pin direction (input or out- put) is still controlled by the da ta direction register (ddr) for th e port pin. the data direction register bit for the oc0a pin (ddr_oc0a) must be set as output before the oc0a value is vis- ible on the pin. the port override function is independent of the w aveform generation mode. the design of the output compare pin logic allows initialization of the oc0a state before the output is enabled. note that some com0a1:0 bit settings are reserved for certain modes of operation. see ?register description? on page 105. 14.6.1 compare output mode and waveform generation the w aveform generator uses the com0a1:0 bits differently in normal, ctc, and p w m modes. for all modes, setting the com0a1:0 = 0 tells the w aveform generator that no action on the oc0a register is to be performed on the next compare match. for compare output actions in the non-p w m modes refer to table 14-3 on page 106 . for fast p w m mode, refer to table 14- 4 on page 106 , and for phase correct p w m refer to table 14-5 on page 106 . port ddr dq dq ocn pin ocnx dq waveform generator comnx1 comnx0 0 1 data b u s focn clk i/o 99 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 a change of the com0a1:0 bits st ate will have effect at the first compare match after the bits are written. for non-p w m modes, the action can be forced to have immediate effect by using the foc0a strobe bits. 14.7 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the w aveform generation mode ( w gm01:0) and compare output mode (com0a1:0) bits. the compare output mode bits do not affect the counting sequence, while the w aveform generation mode bits do. the com0a1:0 bits control whether the p w m output generated should be inverted or not (inverted or non-inverted p w m). for non-p w m modes the com0a1:0 bits control whether the output should be set, cleared, or toggled at a compare match ( see ?compare match output unit? on page 98. ). for detailed timing information refer to figure 14-8 , figure 14-9 , figure 14-10 and figure 14-11 in ?timer/counter timing diagrams? on page 103 . 14.7.1 normal mode the simplest mode of operation is the normal mode ( w gm01:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 8-bit value (top = 0xff) and then restarts from the bot- tom (0x00). in normal o peration the timer/counter overflow flag (tov0) will be set in the same timer clock cycle as the tcnt0 becomes zero. the tov0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov0 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the out- put compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 14.7.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode ( w gm01:0 = 2), the ocr0a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt0) matches the ocr0a. the ocr0a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 14-5 . the counter value (tcnt0) increases until a compare match occurs between tcnt0 and ocr0a, and then counter (tcnt0) is cleared. 100 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 14-5. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocf0a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a va lue close to bottom when the counter is run- ning with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr0a is lower than the current value of tcnt0, the counter will miss the compar e match. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the oc0a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com0a1:0 = 1). the oc0a value will not be visible on the port pin unless the data direction for the pin is set to output. the waveform ge nerated will have a ma ximum frequency of f oc0 = f clk_i/o /2 when ocr0a is set to zero (0x00). the waveform frequency is defined by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tov0 flag is set in the same timer clock cycle that the counter counts from max to 0x00. 14.7.3 fast pwm mode the fast pulse w idth modulation or fast p w m mode ( w gm01:0 = 3) provides a high frequency p w m waveform generation option. the fast p w m differs from the other p w m option by its sin- gle-slope operation. the counter counts from bottom to max then restarts from bottom. in non-inverting compare output mode, the output compare (oc0a) is cleared on the compare match between tcnt0 and ocr0a, and set at bottom. in inverting compare output mode, the output is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast p w m mode can be twice as high as the phase correct p w m mode that use dual-slope operation. this high frequency makes the fast p w m mode well suited for power regulation, rectification, and dac app lications. high frequency a llows physically small sized external components (coils, capacitors), and therefore reduces total system cost. in fast p w m mode, the counter is incremented until the counter value matches the max value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast p w m mode is shown in figure 14-6 . the tcnt0 value is in the timing diagram shown as a his- togram for illustrating the single-slope operation. the diagram includes non-inverted and inverted p w m outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0a and tcnt0. tcntn ocn (toggle) ocnx interrupt flag s et 1 4 period 2 3 (comnx1:0 = 1) f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------- - = 101 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 14-6. fast p w m mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches max. if the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. in fast p w m mode, the compare unit allows generation of p w m waveforms on the oc0a pin. setting the com0a1:0 bits to two will produce a non-inverted p w m and an inverted p w m output can be generated by setting the com0a1:0 to three (see table 14-4 on page 106 ). the actual oc0a value will only be visible on the port pin if the data direction for the port pin is set as out- put. the p w m waveform is generated by setting (or clearing) the oc0a register at the compare match between ocr0a and tcnt0, and clearing (or setting) the oc0a register at the timer clock cycle the counter is cleared (changes from max to bottom). the p w m frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represents special cases when generating a p w m waveform output in the fast p w m mode. if the ocr0a is set equal to bottom, the output will be a narrow spike for each max+1 timer clock cycle. setting the ocr0a equal to max will result in a constantly high or low output (depending on the polarity of the output set by the com0a1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast p w m mode can be achieved by set- ting oc0a to toggle its logical level on each compare match (com0a1:0 = 1). the waveform generated will have a maximum frequency of f oc0 = f clk_i/o /2 when ocr0a is set to zero. this feature is similar to the oc0a toggle in ctc mode, except the double buffer feature of the out- put compare unit is enabled in the fast p w m mode. 14.7.4 phase correct pwm mode the phase correct p w m mode ( w gm01:0 = 1) provides a high resolution phase correct p w m waveform generation option. the phase correct p w m mode is based on a dual-slope operation. the counter counts repeatedly from bottom to max and then from max to bottom. in non- inverting compare output mode, the output compare (oc0a) is cleared on the compare match between tcnt0 and ocr0a while upcounting, and set on the compare match while down- counting. in inverting output compare mode, the operation is inverted. the dual-slope operation tcntn ocrnx update and tovn interrupt flag s et 1 period 2 3 ocn ocn (comnx1:0 = 2) (comnx1:0 = 3 ) ocrnx interrupt flag s et 4 5 6 7 f ocnxpwm f clk_i/o n 256 ? ------------------ = 102 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 has lower maximum operation frequency than single slope operation. however, due to the sym- metric feature of the dual-slope p w m modes, these modes are preferred for motor control applications. the p w m resolution for the phase correct p w m mode is fixed to eight bits. in phase correct p w m mode the counter is incremented until the counter value matches max. w hen the counter reaches max, it changes the count direction. the tcnt0 value will be equal to max for one timer clock cycle. the timing diagram for the phase correct p w m mode is shown on figure 14-7 . the tcnt0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and inverted p w m outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0a and tcnt0. figure 14-7. phase correct p w m mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct p w m mode, the compare unit allows generation of p w m waveforms on the oc0a pin. setting the com0a1:0 bits to two will produce a non-inverted p w m. an inverted p w m output can be generated by setting the com0a1:0 to three (see table 14-5 on page 106 ). the actual oc0a value will only be visible on the port pin if the data direction for the port pin is set as output. the p w m waveform is generated by clearing (or setting) the oc0a register at the compare match between ocr0a and tcnt0 when the counter increments, and setting (or clearing) the oc0a register at compare match between ocr0a and tcnt0 when the counter decrements. the p w m frequency for the output when using phase correct p w m can be calcu- lated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represent special cases when generating a p w m waveform output in the phase correct p w m mode. if the ocr0a is set equal to bottom, the tovn interrupt flag s et ocnx interrupt flag s et 1 2 3 tcntn period ocn ocn (comnx1:0 = 2) (comnx1:0 = 3 ) ocrnx update f ocnxpcpwm f clk_i/o n 510 ? ------------------ = 103 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 output will be continuously low an d if set equal to max the output will be continuously high for non-inverted p w m mode. for inverted p w m the output will have th e opposite logic values. at the very start of period 2 in figure 14-7 ocn has a transition from high to low even though there is no compare match. the point of this transition is to guarantee symmetry around bot- tom. there are two cases that give a transition without compare match. ? ocr0a changes its value from max, like in figure 14-7 . w hen the ocr0a value is max the ocn pin value is the same as the result of a down-counting compare match. to ensure symmetry around bottom the ocn value at max must correspond to the result of an up- counting compare match. ? the timer starts counting from a value higher than the one in ocr0a, and for that reason misses the compare match and hence the ocn change that would have happened on the way up. 14.8 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t0 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set. figure 14-8 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max va lue in all modes other than phase correct p w m mode. figure 14-8. timer/counter timing diagram, no prescaling figure 14-9 shows the same timing data, but with the prescaler enabled. figure 14-9. timer/counter timing dia gram, with prescaler (f clk_i/o /8) figure 14-10 shows the setting of ocf0a in all modes except ctc mode. clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o / 8 ) 104 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 14-10. timer/counter timing diagram, setting of ocf0a, with prescaler (f clk_i/o /8) figure 14-11 shows the setting of ocf0a and the clearing of tcnt0 in ctc mode. figure 14-11. timer/counter timing diagram, clear timer on compare match mode, with pres- caler (f clk_i/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o / 8 ) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o / 8 ) 105 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 14.9 register description 14.9.1 tccr0a ? timer/counter control register a ? bit 7 ? foc0a: force output compare a the foc0a bit is only active when the w gm00 bit specifies a non-p w m mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr0a is written when operating in p w m mode. w hen writing a logical one to the foc0a bit, an immediate com- pare match is forced on the w aveform generation unit. the oc0a output is changed according to its com0a1:0 bits setting. note that the foc0a bit is implemented as a strobe. therefore it is the value present in the com0a1:0 bits that determines the effect of the forced compare. a foc0a strobe will not gen erate any interrupt, nor will it cl ear the timer in ctc mode using ocr0a as top. the foc0a bit is always read as zero. ? bit 6, 3 ? wgm01:0: waveform generation mode these bits control the counting sequence of the counter, the source for the maximum (top) counter value, and what type of waveform generation to be used. modes of operation supported by the timer/counter unit are: normal mode, clear timer on compare match (ctc) mode, and two types of pulse w idth modulation (p w m) modes. see table 14-2 and ?modes of operation? on page 99 . note: 1. the ctc0 and p w m0 bit definition names are now obsolete. use the w gm01:0 definitions. however, the functionality and location of these bits are compatible with previous versions of the timer. ? bit 5:4 ? com0a1:0: compare match output mode these bits control the output compare pin (oc0a) behavior. if one or both of the com0a1:0 bits are set, the oc0a output overrides the normal po rt functionality of the i/o pin it is connected to. however, note that the data direction r egister (ddr) bit corresponding to the oc0a pin must be set in order to enable the output driver. bit 76543210 0x24 (0x44) foc0a wgm00 com0a1 com0a0 wgm01 cs02 cs01 cs00 tccr0a read/ w rite w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 table 14-2. w aveform generation mode bit description (1) mode wgm01 (ctc0) wgm00 (pwm0) timer/counter mode of operation top update of ocr0a at tov0 flag set on 0 0 0 normal 0xff immediate max 10 1p w m, phase correct 0xff top bottom 2 1 0 ctc ocr0a immediate max 31 1fast p w m0xffbottommax 106 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 w hen oc0a is connected to the pin, the f unction of the com0a1:0 bits depends on the w gm01:0 bit setting. table 14-3 shows the com0a1:0 bit functionality when the w gm01:0 bits are set to a normal or ctc mode (non-p w m). table 14-4 shows the com0a1:0 bit functionality when the w gm01:0 bits are set to fast p w m mode. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at bottom. see ?fast p w m mode? on page 100 for more details. table 14-5 shows the com0a1:0 bit functionality when the w gm01:0 bits are set to phase cor- rect p w m mode. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct p w m mode? on page 101 for more details. ? bit 2:0 ? cs02:0: clock select the three clock select bits select the clock source to be used by the timer/counter. table 14-3. compare output mode, non-p w m mode com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc0a on compare match 1 0 clear oc0a on compare match 1 1 set oc0a on compare match table 14-4. compare output mode, fast p w m mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01reserved 10 clear oc0a on compare match, set oc0a at bottom (non-inverting mode) 11 set oc0a on compare match, clear oc0a at bottom (inverting mode) table 14-5. compare output mode, phase correct p w m mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01reserved 10 clear oc0a on compare match when up-counting. set oc0a on compare match when down counting. 11 set oc0a on compare match when up-counting. clear oc0a on compare match when down counting. 107 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 if external pin modes are used for the timer/counter0, transitions on the t0 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 14.9.2 tcnt0 ? timer/counter register the timer/counter register gives direct ac cess, both for read and write operations, to the timer/counter unit 8-bit counter. w riting to the tcnt0 register blocks (removes) the compare match on the following timer clock. modifying the counter (tcnt0) while the counter is running, introduces a risk of missing a compare match between tcnt0 and the ocr0a register. 14.9.3 ocr0a ? output compare register a the output compare register a contains an 8-bi t value that is continuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0a pin. 14.9.4 timsk0 ? timer/counter 0 interrupt mask register ? bit 1 ? ocie0a: timer/counter0 output compare match a interrupt enable w hen the ocie0a bit is written to one, and the i-bit in the status register is set (one), the timer/counter0 compare match a interrupt is enabled. the corresponding interrupt is executed table 14-6. clock select bit description cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped) 001clk i/o /(no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin. clock on falling edge. 1 1 1 external clock source on t0 pin. clock on rising edge. bit 76543210 0x26 (0x46) tcnt0[7:0] tcnt0 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x27 (0x47) ocr0a[7:0] ocr0a read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x6e) ? ? ? ? ? ?ocie0atoie0timsk0 read/ w rite rrrrrrr/ w r/ w initial value00000000 108 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 if a compare match in timer/coun ter0 occurs, i.e., when the ocf0a bit is set in the timer/coun- ter 0 interrupt flag register ? tifr0. ? bit 0 ? toie0: timer/counter0 overflow interrupt enable w hen the toie0 bit is written to one, and the i-bit in the status register is set (one), the timer/counter0 overflow interrupt is enabled. the corresponding interrupt is executed if an overflow in timer/counter0 occurs, i.e., when the tov0 bit is set in the timer/counter 0 inter- rupt flag register ? tifr0. 14.9.5 tifr0 ? timer/counter 0 interrupt flag register ? bit 1 ? ocf0a: output compare flag 0 a the ocf0a bit is set (one) when a compare match occurs between the timer/counter0 and the data in ocr0a ? output compare register0. ocf0a is cleared by hardware when executing the corresponding interrupt handling vector. alter natively, ocf0a is cleared by writing a logic one to the flag. w hen the i-bit in sreg, ocie0a (timer/counter0 compare match interrupt enable), and ocf0a are set (one), the timer/counter0 compare match interrupt is executed. ? bit 0 ? tov0: timer/counter0 overflow flag the bit tov0 is set (one) when an overflow occu rs in timer/counter0. tov0 is cleared by hard- ware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logic one to the flag. w hen the sreg i-bit, toie0 (timer/counter0 overflow inter- rupt enable), and tov0 are set (one), the timer/ counter0 overflow interrupt is executed. in phase correct p w m mode, this bit is set when timer/ counter0 changes counting direction at 0x00. bit 76543210 0x15 (0x35) ? ? ? ? ? ?ocf0a tov0 tifr0 read/ w rite rrrrrrr/ w r/ w initial value 0 0 0 0 0 0 0 0 109 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 15. 16-bit timer/counter1 15.1 features ? true 16-bit design (i.e., allows 16-bit pwm) ? two independent output compare units ? double buffered outp ut compare registers ? one input capture unit ? input capture noise canceler ? clear timer on compare match (auto reload) ? glitch-free, phase correct pu lse width modulator (pwm) ? variable pwm period ? frequency generator ? external event counter ? four independent interrupt sources (tov1, ocf1a, ocf1b, and icf1) 15.2 overview the 16-bit timer/counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. most register and bit references in this sec- tion are written in general form. a lower case ?n? replaces the timer/counter number, and a lower case ?x? replaces the output compare unit number. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt1 for accessing timer/counter1 counter value and so on. a simplified block diagram of the 16-bit timer/counter is shown in figure 15-1 . for the actual placement of i/o pins, refer to ?64a (tqfp)and 64m1 (qfn/mlf) pinout atmega165a/atmega165pa/atmega325a/atmega325pa/atmega645a/atmega645p? on page 2 . cpu accessible i/o registers, including i /o bits and i/o pins, are shown in bold. the device-specific i/o register and bit locations are listed in the ?register description? on page 130 . the prtim1 bit in ?prr ? power reduction register? on page 45 must be written to zero to enable timer/counter1 module 110 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 15-1. 16-bit timer/counter block diagram (1) note: 1. refer to figure 1-1 on page 2 and figure 13-5 on page 74 for timer/counter1 pin placement and description. 15.2.1 registers the timer/counter (tcnt1), output compare registers (ocr1a/b), and input capture regis- ter (icr1) are all 16-bit registers. special procedures must be followed when accessing the 16- bit registers. these procedures are described in the section ?accessing 16-bit registers? on page 111 . the timer/counter co ntrol registers (tccr1a/b) are 8-bit registers and have no cpu access restrictions. interrupt requests (abbrevi ated to int.req. in the figure) signals are all visible in the timer interrupt flag register (tifr1). all interrupts are individually masked with the timer interrupt mask register (timsk1). tifr1 and timsk1 are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the t1 pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t 1 ). the double buffered output compare registers (ocr1a/b) are compared with the timer/coun- ter value at all time. the result of the compare can be used by the w aveform generator to generate a p w m or variable frequency output on the output compare pin (oc1a/b). see ?out- put compare units? on page 118. . the compare match event will also set the compare match flag (ocf1a/b) which can be used to generate an output compare interrupt request. clock s elect timer/counter data b u s ocrna ocrnb icrn = = tcntn waveform generation waveform generation ocna ocnb noise canceler icpn = fixed top values edge detector control logic = 0 top bottom count clear direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) icfn (int.req.) tccrna tccrnb ( from analog comparator ouput ) tn edge detector ( from prescaler ) clk tn 111 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 the input capture register can capture the timer/ counter value at a given external (edge trig- gered) event on either the input capture pin (icp1) or on the analog comparator pins ( see ?ac - analog comparator? on page 210. ) the input capture unit includes a digital filtering unit (noise canceler) for reducing the chance of capturing noise spikes. the top value, or maximum timer/counter value, can in some modes of operation be defined by either the ocr1a register, the icr1 register, or by a set of fixed values. w hen using ocr1a as top value in a p w m mode, the ocr1a register can not be used for generating a p w m output. however, the top va lue will in this case be doub le buffered allowing the top value to be changed in run time. if a fixed top value is required, the icr1 register can be used as an alternative, freeing the ocr1a to be used as p w m output. 15.2.2 definitions the following definitions are used extensively throughout the section: 15.2.3 compatibility the 16-bit timer/counter has been updated and impr oved from previous versions of the 16-bit avr timer/counter. this 16-bit timer/counter is fully compatible with the earlier version regarding: ? all 16-bit timer/counter related i/o register address locations, including timer interrupt registers. ? bit locations inside all 16-bit timer/counter registers, including timer interrupt registers. ? interrupt vectors. the following control bits have changed name, but have same functionality and register location: ?p w m10 is changed to w gm10. ?p w m11 is changed to w gm11. ? ctc1 is changed to w gm12. the following bits are added to the 16-bit timer/counter control registers: ? foc1a and foc1b are added to tccr1c. ? w gm13 is added to tccr1b. the 16-bit timer/counter has improvements that will affect the compatibility in some special cases. 15.3 accessing 16-bit registers the tcnt1, ocr1a/b, and icr1 are 16-bit registers that can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or write operations. each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. the same temporary register is shared between all 16-bit registers within each 16-bit timer. accessing the low byte triggers the 16-bit read or write operation. w hen the low byte of a table 15-1. definition of timer/counter values bottom the counter reaches the bottom when it becomes 0x0000. max the counter reaches its max imum when it becomes 0xffff (decimal 65535). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be one of the fixed values: 0x00ff, 0x01ff, or 0x03ff, or to the value stored in the ocr1a or icr1 register. the assignment is dependent of the m ode of operation. 112 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 16-bit register is written by the cpu, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. w hen the low byte of a 16-bit register is read by the cpu, the high by te of the 16-bit register is copied into the tempo- rary register in the same clock cycle as the low byte is read. not all 16-bit accesses uses the temporary register for the high byte. reading the ocr1a/b 16- bit registers does not involve using the temporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before the high byte. the following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for accessing the ocr1a/b and icr1 registers. note that when using ?c?, the compiler handles the 16-bit access. note: 1. see ?about code examples? on page 9. the assembly code example returns the tcnt1 value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer regis- ters, then the result of the a ccess outside the interrupt will be corrupted. theref ore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. the following code examples show how to do an atomic read of the tcnt1 register contents. reading any of the ocr1a/b or icr1 registers can be done by using the same principle. assembly code examples (1) ... ; set tcnt 1 to 0x01ff ldi r17,0x01 ldi r16,0xff out tcnt 1 h,r17 out tcnt 1 l,r16 ; read tcnt 1 into r17:r16 in r16,tcnt 1 l in r17,tcnt 1 h ... c code examples (1) unsigned int i; ... /* set tcnt 1 to 0x01ff */ tcnt 1 = 0x1ff; /* read tcnt 1 into i */ i = tcnt 1 ; ... 113 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 note: 1. see ?about code examples? on page 9. the assembly code example returns the tcnt1 value in the r17:r16 register pair. the following code examples show how to do an atomic write of the tcnt1 register contents. w riting any of the ocr1a/b or icr1 register s can be done by using the same principle. assembly code example (1) tim16_readtcnt 1 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcnt 1 into r17:r16 in r16,tcnt 1 l in r17,tcnt 1 h ; restore global interrupt flag out sreg,r18 ret c code example (1) unsigned int tim16_readtcnt 1 ( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ __disable_interrupt(); /* read tcnt 1 into i */ i = tcnt 1 ; /* restore global interrupt flag */ sreg = sreg; return i; } 114 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 note: 1. see ?about code examples? on page 9. the assembly code example requires that the r17:r16 register pair contains the value to be writ- ten to tcnt1. 15.3.1 reusing the temporary high byte register if writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described previously also applies in this case. 15.4 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs12:0) bits located in the timer/counter control register b (tccr1b). for details on clock sources and prescaler, see ?timer/counter0 and timer/counter1 prescalers? on page 137 . assembly code example (1) tim16_writetcnt 1 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcnt 1 to r17:r16 out tcnt 1 h,r17 out tcnt 1 l,r16 ; restore global interrupt flag out sreg,r18 ret c code example (1) void tim16_writetcnt 1 ( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ __disable_interrupt(); /* set tcnt 1 to i */ tcnt 1 = i; /* restore global interrupt flag */ sreg = sreg; } 115 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 15.5 counter unit the main part of the 16-bit timer/counter is th e programmable 16-bit bi-directional counter unit. figure 15-2 shows a block diagram of the counter and its surroundings. figure 15-2. counter unit block diagram signal description (internal signals): count increment or decrement tcnt1 by 1. direction select between increment and decrement. clear clear tcnt1 (set all bits to zero). clk t 1 timer/counter clock. top signalize that tcnt1 has reached maximum value. bottom signalize that tcnt1 has re ached minimum value (zero). the 16-bit counter is mapped into two 8-bit i/o memory locations: counter high (tcnt1h) con- taining the upper eight bits of the counter, and counter low (tcnt1l) containing the lower eight bits. the tcnt1h register can only be indirectly accessed by the cpu. w hen the cpu does an access to the tcnt1h i/o location, the cpu accesses the high byte temporary register (temp). the temporary register is updated with the tcnt1h value when the tcnt1l is read, and tcnt1h is updated with the temporary register va lue when tcnt1l is written. this allows the cpu to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. it is important to notice that there are special cases of writing to the tcnt1 register when the counter is counting that will gi ve unpredictable results. the s pecial cases are described in the sections where they are of importance. depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t 1 ). the clk t 1 can be generated from an external or internal clock source, selected by the clock select bits (cs12:0). w hen no clock source is selected (cs12:0 = 0) the timer is stopped. however, the tcnt1 value can be accessed by the cpu, independent of whether clk t 1 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the waveform generation mode bits ( w gm13:0) located in the timer/counter control registers a and b (tccr1a and tccr1b). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs oc1x. for more details about advanced counting sequences and waveform generation, see ?modes of operation? on page 121 . the timer/counter overflow flag (tov1) is set according to the mode of operation selected by the w gm13:0 bits. tov1 can be used for generating a cpu interrupt. temp ( 8 -bit) data b u s ( 8 -bit) tcntn (16-bit counter) tcntnh ( 8 -bit) tcntnl ( 8 -bit) control logic count clear direction tovn (int.req.) clock s elect top bottom tn edge detector ( from prescaler ) clk tn 116 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 15.6 input capture unit the timer/counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. the external signal indicating an event, or mul- tiple events, can be applied via the icp1 pin or al ternatively, via the analog-comparator unit. the time-stamps can then be used to calculate frequenc y, duty-cycle, and other features of the sig- nal applied. alternatively the time-stamps can be used for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 15-3 . the elements of the block diagram that are not directly a part of the input capture unit are gray shaded. the small ?n? in register and bit names indicates the timer/counter number. figure 15-3. input capture unit block diagram w hen a change of the logic level (an event) occurs on the input capture pin (icp1), alternatively on the analog comparator output (aco), and this change confirms to the setting of the edge detector, a capture will be triggered. w hen a capture is triggered, the 16-bit value of the counter (tcnt1) is written to the input capture register (icr1). the input capture flag (icf1) is set at the same system clock as the tcnt1 value is copi ed into icr1 register. if enabled (icie1 = 1), the input capture flag generates an input capture interrupt. the icf1 flag is automatically cleared when the interrupt is executed. alternatively the icf1 flag can be cleared by software by writing a logical one to its i/o bit location. reading the 16-bit value in the input capture register (icr1) is done by first reading the low byte (icr1l) and then the high byte (icr1h). w hen the low byte is read the high byte is copied into the high byte temporary register (temp). w hen the cpu reads the icr1h i/o location it will access the temp register. the icr1 register can only be written when using a w aveform generation mode that utilizes the icr1 register for defining the counter?s top value. in these cases the waveform genera- tion mode ( w gm13:0) bits must be set before the top value can be written to the icr1 register. w hen writing the icr1 register the high byte must be written to the icr1h i/o location before the low byte is written to icr1l. icfn (int.req.) analog comparator write icrn (16-bit register) icrnh ( 8 -bit) noise canceler icpn edge detector temp ( 8 -bit) data b u s ( 8 -bit) icrnl ( 8 -bit) tcntn (16-bit counter) tcntnh ( 8 -bit) tcntnl ( 8 -bit) acic* icnc ices aco* 117 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 for more information on how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 111 . 15.6.1 input capture trigger source the main trigger source for the input capture unit is the input capture pin (icp1). timer/counter1 can alternatively use the analog comparator output as trigger source for the input capture unit. the analog comparator is selected as trigger source by setting the analog comparator input capture (acic) bit in the analog comparator control and status register (acsr). be aware that changing trigger source can trigger a capture. the input capture flag must therefore be cleared after the change. both the input capture pin (icp1) and the analog comparator output (aco) inputs are sampled using the same technique as for the t1 pin ( figure 16-1 on page 137 ). the edge detector is also identical. however, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases t he delay by four system clock cycles. note that the input of the noise canceler and edge detector is always enabled unless the timer/counter is set in a w ave- form generation mode that uses icr1 to define top. an input capture can be trigger ed by software by controlling the port of the icp1 pin. 15.6.2 noise canceler the noise canceler improves noise immunity by using a simple digital filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (icnc1) bit in timer/counter control register b (tccr1b). w hen enabled the noise canceler introduces addi- tional four system clock cycles of delay from a change applied to the input, to the update of the icr1 register. the noise canceler uses the sy stem clock and is therefore not affected by the prescaler. 15.6.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in th e icr1 register before the nex t event occurs, the icr1 will be overwritten with a new value. in this case the result of the ca pture will be incorrect. w hen using the input capture interrupt, the icr1 register should be read as early in the inter- rupt handler routine as possible. even though the input capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. using the input capture unit in any mode of operation when the top value (resolution) is actively changed during operation, is not recommended. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as possible after the icr1 register has been read. after a change of the edge, the input capture flag (icf1) must be cleared by software (writing a logical one to the i/o bit location). for measuring frequency only, the clearing of the icf1 flag is not required (if an interrupt handler is used). 118 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 15.7 output compare units the 16-bit comparator continuously compares tcnt1 with the output compare register (ocr1x). if tcnt equals ocr1x the comparator signals a match. a match will set the output compare flag (ocf1x) at the next timer clock cycle. if enabled (ocie1x = 1), the output com- pare flag generates an output compare interrupt. the ocf1x flag is automatically cleared when the interrupt is executed. alternatively the ocf1x flag can be cleared by software by writ- ing a logical one to its i/o bit location. the w aveform generator uses the match signal to generate an output according to operating mode set by the waveform generation mode ( w gm13:0) bits and compare output mode (com1x1:0) bits. the top and bottom signals are used by the w aveform generator for handling the special cases of the extreme values in some modes of operation ( see ?modes of operation? on page 121. ) a special feature of output compare unit a allows it to define the timer/counter top value (i.e., counter resolution). in addition to the counter resolution, the top value defines the period time for waveforms generated by the w aveform generator. figure 15-4 shows a block diagram of the output compare unit. the small ?n? in the register and bit names indicates the device number (n = 1 for timer/counter 1), and the ?x? indicates output compare unit (a/b). the elements of the block diagram that are not directly a part of the output compare unit are gray shaded. figure 15-4. output compare unit, block diagram the ocr1x register is double buffered when using any of the twelve pulse width modulation (p w m) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocr1x com- pare register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical p w m pulses, thereby making the out- put glitch-free. the ocr1x register access may seem complex, but this is not case. w hen the double buffering is enabled, the cpu has access to the ocr1x buffer register, and if double buffering is dis- ocfnx (int.req.) = (16-bit comparator ) ocrnx buffer (16-bit register) ocrnxh buf. ( 8 -bit) ocnx temp ( 8 -bit) data b u s ( 8 -bit) ocrnxl buf. ( 8 -bit) tcntn (16-bit counter) tcntnh ( 8 -bit) tcntnl ( 8 -bit) comnx1:0 wgmn3:0 ocrnx (16-bit register) ocrnxh ( 8 -bit) ocrnxl ( 8 -bit) waveform generator top bottom 119 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 abled the cpu will access the ocr1x directly. the content of the ocr1x (buffer or compare) register is only changed by a write operation (the timer/counter does not update this register automatically as the tcnt1 and icr1 register). therefore ocr1x is not read via the high byte temporary register (temp). however, it is a good practice to read the low byte first as when accessing other 16-bit registers. w riting the ocr1x registers must be done via the temp reg- ister since the compare of all 16 bits is done continuously. the high byte (ocr1xh) has to be written first. w hen the high byte i/o location is written by the cpu, the temp register will be updated by the value written. then when the low by te (ocr1xl) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the ocr1x bu ffer or ocr1x compare register in the same system clock cycle. for more information of how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 111 . 15.7.1 force output compare in non-p w m w aveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc1x) bit. forcing compare match will not set the ocf1x flag or reload/clear the timer, but the oc1x pin will be updated as if a real compare match had occurred (the comx1:0 bits settings define whether the oc1x pin is set, cleared or toggled). 15.7.2 compare match bloc king by tcnt1 write all cpu writes to the tcnt1 register will block any compare match that o ccurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocr1x to be initialized to the same value as tcnt1 without triggering an inte rrupt when the timer/counter clock is enabled. 15.7.3 using the output compare unit since writing tcnt1 in any mode of operation will block all comp are matches for one timer clock cycle, there are risks involved when changing tcnt1 when using any of the output compare units, independent of whether the timer/counter is running or not. if the value written to tcnt1 equals the ocr1x value, the compare match will be missed, resulting in incorrect waveform generation. do not write the tcnt1 equal to top in p w m modes with variable top values. the compare match for the top will be ignored and the counter will c ontinue to 0xffff. similarly, do not write the tcnt1 value equal to bottom when the counter is down counting. the setup of the oc1x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc1x value is to use the force output com- pare (foc1x) strobe bits in normal mode. the oc1x register keeps its value even when changing between w aveform generation modes. be aware that the com1x1:0 bits are not doubl e buffered together with the compare value. changing the com1x1:0 bits will take effect immediately. 15.8 compare match output unit the compare output mode (com1x1:0) bits have two functions. the w aveform generator uses the com1x1:0 bits for defining the output compare (oc1x) state at the next compare match. secondly the com1x1:0 bits control the oc1x pin output source. figure 15-5 shows a simplified schematic of the logic affected by the com1x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com1x1:0 bits are shown. w hen referring to the oc1x state, the reference is for the internal oc1x register, not the oc1x pin. if a system reset occur, the oc1x register is reset to ?0?. 120 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 15-5. compare match output unit, schematic the general i/o port function is overridden by the output compare (oc1x) from the w aveform generator if either of the com1x1:0 bits are set. however, the oc1x pin direction (input or out- put) is still controlled by the data direction register (ddr) for the port pin. the data direction register bit for the oc1x pin (ddr_oc1x) must be set as output before the oc1x value is visi- ble on the pin. the port override func tion is generally independent of the w aveform generation mode, but there are some exceptions. refer to table 15-2 , table 15-3 and table 15-4 for details. the design of the output compare pin logic allows initialization of the oc1x state before the out- put is enabled. note that some com1x1:0 bi t settings are reserved for certain modes of operation. see ?register description? on page 130. the com1x1:0 bits have no effect on the input capture unit. 15.8.1 compare output mode and waveform generation the w aveform generator uses the com1x1:0 bits differently in normal, ctc, and p w m modes. for all modes, setting the com1x1:0 = 0 tells the w aveform generator that no action on the oc1x register is to be performed on the next compare match. for compare output actions in the non-p w m modes refer to table 15-2 on page 130 . for fast p w m mode refer to table 15-3 on page 130 , and for phase correct and phase and frequency correct p w m refer to table 15-4 on page 131 . a change of the com1x1:0 bits st ate will have effect at the first compare matc h after the bits are written. for non-p w m modes, the action can be forced to have immediate effect by using the foc1x strobe bits. port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data b u s focnx clk i/o 121 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 15.9 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode ( w gm13:0) and compare output mode (com1x1:0) bits. the compare output mode bits do not affect the counting sequence, while the w aveform generation mode bits do. the com1x1:0 bits control whether the p w m out- put generated should be inverted or not (inverted or non-inverted p w m). for non-p w m modes the com1x1:0 bits control whether the output should be set, cleared or toggle at a compare match ( see ?compare match output unit? on page 119. ) for detailed timing information refer to ?timer/counter timing diagrams? on page 128 . 15.9.1 normal mode the simplest mode of operation is the normal mode ( w gm13:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from the bottom (0x0000). in normal operation the timer/counter overflow flag (tov1) will be set in the same timer clock cycle as the tcnt1 become s zero. the tov1 flag in this case behaves like a 17th bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov1 flag, the timer resolution can be increased by soft- ware. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the input capture unit is easy to use in normal mode. however, observe that the maximum interval between the external events must not exceed the resolution of the counter. if the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. the output compare units can be used to generat e interrupts at some given time. using the output compare to gene rate waveforms in norm al mode is not recommended, since this will occupy too much of the cpu time. 15.9.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode ( w gm13:0 = 4 or 12), the ocr1a or icr1 register are used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt1) matches either the ocr1a ( w gm13:0 = 4) or the icr1 ( w gm13:0 = 12). the ocr1a or icr1 define the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the opera- tion of counting external events. the timing diagram for the ctc mode is shown in figure 15-6 . the counter value (tcnt1) increases until a compare match occurs with either ocr1a or icr1, and then counter (tcnt1) is cleared. 122 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 15-6. ctc mode, timing diagram an interrupt can be generated at each time the counter value reaches the top value by either using the ocf1a or icf1 flag according to the register used to define the top value. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. how- ever, changing the top to a value close to bottom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buff- ering feature. if the new value written to ocr1a or icr1 is lower than the current value of tcnt1, the counter will miss the co mpare match. the counter will then have to count to its max- imum value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. in many cases this feature is not desirable. an al ternative will then be to use the fast p w m mode using ocr1a for defining top ( w gm13:0 = 15) since the ocr1a then will be doub le buffered. for generating a waveform output in ctc mode, the oc1a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com1a1:0 = 1). the oc1a value will not be visible on the port pin unless the data direction for the pin is set to output (ddr_oc1a = 1). th e waveform generated will have a maximum fre- quency of f oc 1 a = f clk_i/o /2 when ocr1a is set to zero (0x0000). the waveform frequency is defined by the following equation: the n variable represents the prescaler factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tov1 flag is set in the same timer clock cycle that the counter counts from max to 0x0000. 15.9.3 fast pwm mode the fast pulse width modulation or fast p w m mode ( w gm13:0 = 5, 6, 7, 14, or 15) provides a high frequency p w m waveform generation option. the fast p w m differs from the other p w m options by its single-slope operation. the counter counts from bottom to top then restarts from bottom. in non-inverting compare output mode, the output compare (oc1x) is cleared on the compare match between tcnt1 and ocr1x, and set at bottom. in inverting compare output mode output is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast p w m mode can be twice as high as the phase cor- rect and phase and frequency correct p w m modes that use dual-slope operation. this high frequency makes the fast p w m mode well suited for power regu lation, rectification, and dac applications. high frequency allows physically sm all sized external com ponents (coils, capaci- tors), hence reduces total system cost. the p w m resolution for fast p w m can be fixed to 8-, 9-, or 10-bit, or defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the max- tcntn ocna (toggle) ocna interrupt flag s et or icfn interrupt flag s et (interrupt on top) 1 4 period 2 3 (comna1:0 = 1) f ocna f clk_i/o 2 n 1 ocrna + () ?? -------------------------------------------------- - = 123 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 imum resolution is 16-bit (icr1 or ocr1a set to max). the p w m resolution in bits can be calculated by using the following equation: in fast p w m mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff ( w gm13:0 = 5, 6, or 7), the value in icr1 ( w gm13:0 = 14), or the value in ocr1a ( w gm13:0 = 15). the counter is then cleared at the following timer clock cycle. the timing diagram for the fast p w m mode is shown in figure 15-7 . the figure shows fast p w m mode when ocr1a or icr1 is used to define top. the tcnt 1 value is in the timing diagram shown as a histogram for illu strating the single-slope operation. the diagram includes non-inverted and inverted p w m outputs. the small horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. the oc1x interrupt flag will be set when a compare match occurs. figure 15-7. fast p w m mode, timing diagram the timer/counter overflow flag (tov1) is set each time the counter reaches top. in addition the oc1a or icf1 flag is set at the same time r clock cycle as tov1 is set when either ocr1a or icr1 is used for defining the top value. if one of the interrupts are enabled, the interrupt han- dler routine can be used for updating the top and compare values. w hen changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcnt1 and the ocr1x. note that when using fixed top values the unused bits are masked to zero when any of the ocr1x registers are written. the procedure for updating icr1 differs from updating ocr1a when used for defining the top value. the icr1 register is not double buffered. this means that if icr1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new icr1 value written is lower than the current va lue of tcnt1. the result will then be that the counter will miss the compare matc h at the top value. the counter will then have to count to the max value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. the ocr1a register however, is double buffered. this feature allows the ocr1a i/o location to be written anytime. w hen the ocr1a i/o location is written the value written will be put into the ocr1a buffer register. th e ocr1a compare register will th en be updated with the value in the buffer register at the next timer clo ck cycle the tcnt1 matches top. the update is done at the same timer clock cycle as the tcnt 1 is cleared and the tov1 flag is set. r fpwm top 1 + () log 2 () log ---------------------------------- - = tcntn ocrnx / top update and tovn interrupt flag s et and ocna interrupt flag s et or icfn interrupt flag s et (interrupt on top) 1 7 period 2 3 4 5 6 8 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3 ) 124 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 using the icr1 register for defining top work s well when using fixed top values. by using icr1, the ocr1a register is free to be used for generating a p w m output on oc1a. however, if the base p w m frequency is actively changed (by ch anging the top value), using the ocr1a as top is clearly a better choice due to its double buffer feature. in fast p w m mode, the compare units allow generation of p w m waveforms on the oc1x pins. setting the com1x1:0 bits to tw o will produce a non-inverted p w m and an inverted p w m output can be generated by setting the com1x1:0 to three (see table on page 130 ). the actual oc1x value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_oc1x). the p w m waveform is generated by setting (or clearing) the oc1x register at the compare match between ocr1x and tcnt1, and clearing (or setting) the oc1x register at the timer clock cycle the counter is cleared (changes from top to bottom). the p w m frequency for the output can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1x register represents special cases when generating a p w m waveform output in the fast p w m mode. if the ocr1x is set equal to bottom (0x0000) the out- put will be a narrow spike for eac h top+1 timer clock cycle. se tting the ocr1x equal to top will result in a const ant high or low output (depending on the polarity of the output set by the com1x1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast p w m mode can be achieved by set- ting oc1a to toggle its logical level on each compare match (com1a1:0 = 1). this applies only if ocr1a is used to define the top value ( w gm1[3:0] = 15). the wave form generated will have a maximum frequency of f oc 1 a = f clk_i/o /2 when ocr1a is set to zero (0x0000). this feature is similar to the oc1a toggle in ctc mode, except the double buffer feature of the output com- pare unit is enabled in the fast p w m mode. 15.9.4 phase correct pwm mode the phase correct pulse width modulation or phase correct p w m mode ( w gm13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct p w m waveform generation option. the phase correct p w m mode is, like the phase and frequency correct p w m mode, based on a dual- slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (oc1x) is cleared on the compare match between tcnt1 and ocr1x while upcounting, and set on the compare match while down counting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope p w m modes, these modes are preferred for motor control applications. the p w m resolution for the phase correct p w m mode can be fixed to 8-, 9-, or 10-bit, or defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the maximum resolution is 16-bit (icr1 or ocr1a set to max). the p w m resolu- tion in bits can be calculated by using the following equation: in phase correct p w m mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff ( w gm13:0 = 1, 2, or 3), the value in icr1 ( w gm13:0 = 10), or the value in ocr1a ( w gm13:0 = 11). the counter has then reached the f ocnxpwm f clk_i/o n 1 top + () ? ---------------------------------- - = r pcpwm top 1 + () log 2 () log ---------------------------------- - = 125 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 top and changes the count direct ion. the tcnt1 value will be equa l to top for one timer clock cycle. the timing diagram for the phase correct p w m mode is shown on figure 15-8 . the figure shows phase correct p w m mode when ocr1a or icr1 is used to define top. the tcnt1 value is in the timing diagram shown as a histogram for illustrati ng the dual-slope operation. the diagram includes non-inverted and inverted p w m outputs. the small horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. the oc1x inter- rupt flag will be set when a compare match occurs. figure 15-8. phase correct p w m mode, timing diagram the timer/counter overflow flag (tov1) is set each time the counter reaches bottom. w hen either ocr1a or icr1 is used for defining the top value, the oc1a or icf1 flag is set accord- ingly at the same timer clock cycle as the ocr1x registers are updated with the double buffer value (at top). the interrupt flags can be used to generate an interrupt each time the counter reaches the top or bottom value. w hen changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcnt1 and the ocr1x. note that when using fixed top values, the unus ed bits are masked to zero when any of the ocr1x registers are written. as the third period shown in figure 15-8 illustrates, changing the top actively while the timer/counter is running in the phase correct mode can result in an unsymmetrical output. the reason for this can be found in the time of update of the ocr1x reg- ister. since the ocr1x update occurs at top, the p w m period starts and ends at top. this implies that the length of the falling slope is determined by the previous top value, while the length of the rising slope is determined by the new top value. w hen these two values differ the two slopes of the period will differ in length. the difference in length gives the unsymmetrical result on the output. it is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the top value while the timer/counter is running. w hen using a static top value there are practically no differences between the two modes of operation. in phase correct p w m mode, the compare units allow generation of p w m waveforms on the oc1x pins. setting the com1x1:0 bits to two will produce a non-inverted p w m and an inverted p w m output can be generated by setting the com1x1:0 to three (see table 15-4 on page 131 ). ocrnx/top update and ocna interrupt flag s et or icfn interrupt flag s et (interrupt on top) 1 2 3 4 tovn interrupt flag s et (interrupt on bottom) tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3 ) 126 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 the actual oc1x value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_oc1x). the p w m waveform is generated by setting (or clearing) the oc1x register at the compare match between ocr1x and tcnt1 when the counter increments, and clearing (or setting) the oc1x register at compare match between ocr1x and tcnt1 when the counter decrements. the p w m frequency for the output when using phase correct p w m can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1x register represent special cases when generating a p w m waveform output in the phase correct p w m mode. if the ocr1x is set equal to bottom the output will be continuously low and if set equal to top the output will be continuously high for non-inverted p w m mode. for inverted p w m the output will have the opposite logic values. if ocr1a is used to define the top value ( w gm1[3:0] = 11) and com1a1:0 = 1, the oc1a out- put will toggle with a 50% duty cycle. 15.9.5 phase and frequency correct pwm mode the phase and frequency correct pulse width modulation, or phase and frequency correct p w m mode ( w gm13:0 = 8 or 9) provides a high resolution phase and frequency correct p w m wave- form generation option. the phase and frequency correct p w m mode is, like the phase correct p w m mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (oc1x) is cleared on the compare match between tcnt1 and ocr1x while upcounting, and set on the compare match while down counting. in inverting compare output mode, the operation is inverted. the dual-slope operation gives a lower maximum operation fre- quency compared to the single-slope operation. howe ver, due to the symmetric feature of the dual-slope p w m modes, these modes are preferred for motor control applications. the main difference between the phase correct, and the phase and frequency correct p w m mode is the time the ocr1x register is up dated by the ocr1x buffer register, (see figure 15- 8 and figure 15-9 ). the p w m resolution for the phase and frequency correct p w m mode can be defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the maximum resolution is 16-bit (icr1 or ocr1a set to max). the p w m resolution in bits can be calculated using the following equation: in phase and frequency correct p w m mode the counter is incremented until the counter value matches either the value in icr1 ( w gm13:0 = 8), or the value in ocr1a ( w gm13:0 = 9). the counter has then reac hed the top and ch anges the count di rection. the tcnt1 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct and frequency correct p w m mode is shown on figure 15-9 . the figure shows phase and frequency correct p w m mode when ocr1a or icr1 is used to define top. the tcnt1 value is in the timing dia- gram shown as a histogram for illustrating the dual-slope operati on. the diagram includes non- inverted and inverted p w m outputs. the small horizontal line marks on the tcnt1 slopes repre- sent compare matches between o cr1x and tcnt1. the oc1x inte rrupt flag will be set when a compare match occurs. f ocnxpcpwm f clk_i/o 2 ntop ?? --------------------------- - = r pfcpwm top 1 + () log 2 () log ---------------------------------- - = 127 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 15-9. phase and frequency correct p w m mode, timing diagram the timer/counter overflow flag (tov1) is set at the same timer clock cycle as the ocr1x registers are updated with the double buffer value (at bottom). w hen either ocr1a or icr1 is used for defining the top value, the oc1a or icf1 flag set when tcnt1 has reached top. the interrupt flags can then be used to generate an interrupt each time the counter reaches the top or bottom value. w hen changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will neve r occur between the tcnt1 and the ocr1x. as figure 15-9 shows the output generated is, in contrast to the phase correct mode, symmetri- cal in all periods. since the ocr1x registers are updated at bottom, the length of the rising and the falling slopes will always be equal. this gives symmetrical output pulses and is therefore frequency correct. using the icr1 register for defining top work s well when using fixed top values. by using icr1, the ocr1a register is free to be used for generating a p w m output on oc1a. however, if the base p w m frequency is actively changed by changing the top value, using the ocr1a as top is clearly a better choice due to its double buffer feature. in phase and frequency correct p w m mode, the compare units allow generation of p w m wave- forms on the oc1x pins. setting the com1x1:0 bits to two will produce a non-inverted p w m and an inverted p w m output can be generated by setting the com1x1:0 to three (see table 15-4 on page 131 ). the actual oc1x value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_oc1x). the p w m waveform is generated by setting (or clearing) the oc1x register at the compare match between ocr1x and tcnt1 when the counter incre- ments, and clearing (or setting) the oc1x register at compare match between ocr1x and tcnt1 when the counter decrements. the p w m frequency for the output when using phase and frequency correct p w m can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). ocrnx/top updateand tovn interrupt flag s et (interrupt on bottom) ocna interrupt flag s et or icfn interrupt flag s et (interrupt on top) 1 2 3 4 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3 ) f ocnxpfcpwm f clk_i/o 2 ntop ?? --------------------------- - = 128 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 the extreme values for the ocr1x register represents special cases when generating a p w m waveform output in the phase and frequency correct p w m mode. if the ocr1x is set equal to bottom the output will be contin uously low and if se t equal to top th e output will be set to high for non-inverted p w m mode. for inverted p w m the output will have the opposite logic val- ues. if ocr1a is used to define the top value ( w gm1[3:0] = 9) and com1a1:0 = 1, the oc1a output will toggle with a 50% duty cycle. 15.10 timer/counte r timing diagrams the timer/counter is a synchronous design and the timer clock (clk t1 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set, and when the ocr1x register is updated with the ocr1x buffer value (only for modes utilizing double buffering). figure 15-10 shows a timing diagram for the setting of ocf1x. figure 15-10. timer/counter timing diagram, setting of ocf1x, no prescaling figure 15-11 shows the same timing data, but with the prescaler enabled. figure 15-11. timer/counter timing diagram, setting of ocf1x, with prescaler (f clk_i/o /8) figure 15-12 shows the count sequence clos e to top in various modes. w hen using phase and frequency correct p w m mode the ocr1x register is updated at bottom. the timing diagrams will be the same, but top should be replaced by bottom, top-1 by bottom+1 and so on. the same renaming applies for modes that set the tov1 flag at bottom. clk tn (clk i/o /1) ocfnx clk i/o ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o / 8 ) 129 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 15-12. timer/counter timing diagram, no prescaling figure 15-13 shows the same timing data, but with the prescaler enabled. figure 15-13. timer/counter timing dia gram, with prescaler (f clk_i/o /8) tovn (fpwm) and icfn (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk tn (clk i/o /1) clk i/o tovn (fpwm) and icf n (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o / 8 ) 130 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 15.11 register description 15.11.1 tccr1a ? timer/counter1 control register a ? bit 7:6 ? com1a[1:0]: compare output mode for unit a ? bit 5:4 ? com1b[1:0]: compare output mode for unit b the com1a[1:0] and com1b[1:0] control the output compare pins (oc1a and oc1b respec- tively) behavior. if one or both of the com1a[1:0] bits are written to one, the oc1a output overrides the normal port functionality of the i/o pin it is connected to. if one or both of the com1b[1:0] bit are written to one, the oc1b output overrides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit correspond- ing to the oc1a or oc1b pin must be set in order to enable the output driver. w hen the oc1a or oc1b is connected to the pin, the function of the com1x[1:0] bits is depen- dent of the w gm1[3:0] bits setting... table 15-2 shows the com1x[1:0] bit functionality when the w gm1[3:0] bits are set to a normal or a ctc mode (non-p w m). table 15-3 shows the com1x[1:0] bit functionality when the w gm1[3:0] bits are set to the fast p w m mode. note: 1. a special case occurs when ocr1a/oc r1b equals top and com1a1/com1b1 is set. in this case the compare match is ignored, but the set or clear is done at top. see ?fast p w m mode? on page 122. for more details. bit 7 6 5 4 3 2 1 0 (0x80) com1a1 com1a0 com1b1 com1b0 ? ? wgm11 wgm10 tccr1a read/ w rite r/ w r/ w r/ w r/ w rrr/ w r/ w initial value 0 0 0 0 0 0 0 0 table 15-2. compare output mode, non-p w m com1a1/com1b1 com1a0/com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected. 0 1 toggle oc1a/oc1b on compare match. 10 clear oc1a/oc1b on compare match (set output to low level). 11 set oc1a/oc1b on compare match (set output to high level). table 15-3. compare output mode, fast p w m (1) com1a1/com1b1 com1a0/com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected. 01 w gm1[3:0] = 14 or 15: toggle oc1a on compare match, oc1b disconnected (normal port operation). for all other w gm1 settings, normal port operation, oc1a/oc1b disconnected. 10 clear oc1a/oc1b on compare match, set oc1a/oc1b at bottom (non-inverting mode) 11 set oc1a/oc1b on compare match, clear oc1a/oc1b at bottom (inverting mode) 131 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 table 15-4 shows the com1x[1:0] bit functionality when the w gm1[3:0] bits are set to the phase correct or the phase and frequency correct, p w m mode. note: 1. a special case occurs when ocr1a/ ocr1b equals top and com1a1/com1b1 is set. see ?phase correct p w m mode? on page 124. for more details. ? bit 1:0 ? wgm1[1:0]: waveform generation mode combined with the w gm1[3:2] bits found in the tccr1b register, these bits control the count- ing sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation to be used, see table 15-5 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and three types of pulse w idth modulation (p w m) modes. ( see ?modes of operation? on page 121. ). table 15-4. compare output mode, phase correct and phase and frequency correct p w m (1) com1a1/com1b1 com1a0/com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected. 01 w gm1[3:0] = 9 or 11: toggle oc1a on compare match, oc1b disconnected (normal port operation). for all other w gm1 settings, normal port operation, oc1a/oc1b disconnected. 10 clear oc1a/oc1b on compare match when up- counting. set oc1a/oc1b on compare match when down counting. 11 set oc1a/oc1b on compare match when up- counting. clear oc1a/oc1b on compare match when down counting. 132 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 note: 1. the ctc1 and p w m1[1:0] bit definition na mes are obsolete. use the w gm 1[2:0] definitions. howeve r, the functionality and location of these bits are compatible with previous versions of the timer. 15.11.2 tccr1b ? timer/counter1 control register b ? bit 7 ? icnc1: input capture noise canceler setting this bit (to one) activates the input capture noise canceler. w hen the noise canceler is activated, the input from the input capture pin (icp1) is filtered. the filter function requires four successive equal valued samples of the icp1 pin for changing its output. the input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled. ? bit 6 ? ices1: input capture edge select this bit selects which edge on the input capture pin (icp1) that is used to trigger a capture event. w hen the ices1 bit is written to zero, a fa lling (negative) edge is used as trigger, and when the ices1 bit is written to one, a risi ng (positive) edge w ill trigger the capture. w hen a capture is triggered according to the ices1 setting, the counter value is copied into the input capture register (icr1). the event will also set the input capture flag (icf1), and this can be used to cause an input capture interrupt, if this interrupt is enabled. table 15-5. w aveform generation mode bit description (1) mode wgm13 wgm12 (ctc1) wgm11 (pwm11) wgm10 (pwm10) timer/counter mode of operation top update of ocr1 x at tov1 flag set on 0 0 0 0 0 normal 0xffff immediate max 10001p w m, phase correct, 8-bit 0x00ff top bottom 20010p w m, phase correct, 9-bit 0x01ff top bottom 30011p w m, phase correct, 10-bit 0x03ff top bottom 4 0 1 0 0 ctc ocr1a immediate max 50101fast p w m, 8-bit 0x00ff bottom top 60110fast p w m, 9-bit 0x01ff bottom top 70111fast p w m, 10-bit 0x03ff bottom top 81000 p w m, phase and frequency correct icr1 bottom bottom 91001 p w m, phase and frequency correct ocr1a bottom bottom 101010p w m, phase correct icr1 top bottom 111011p w m, phase correct ocr1a top bottom 12 1 1 0 0 ctc icr1 immediate max 13 1 1 0 1 (reserved) ? ? ? 14 1 1 1 0 fast p w m icr1 bottom top 15 1 1 1 1 fast p w m ocr1a bottom top bit 7654 3210 (0x81) icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 tccr1b read/ w rite r/ w r/ w rr/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 133 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 w hen the icr1 is used as top va lue (see description of the w gm1[3:0] bits located in the tccr1a and the tccr1b register), the icp1 is disconnected and consequently the input cap- ture function is disabled. ? bit 5 ? reserved this bit is reserved for future use. for ensuring compatibility with future de vices, this bit must be written to zero when tccr1b is written. ? bit 4:3 ? wgm1[3:2]: waveform generation mode see tccr1a register description. ? bit 2:0 ? cs1[2:0]: clock select the three clock select bits select the clock source to be used by the timer/counter, see figure 15-10 and figure 15-11 . if external pin modes are used for the timer/counter1, transitions on the t1 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 15.11.3 tccr1c ? timer/counter1 control register c ? bit 7 ? foc1a: force output compare for unit a ? bit 6 ? foc1b: force output compare for unit b the foc1a/foc1b bits are only active when the w gm1[3:0] bits specifies a non-p w m mode. however, for ensuring compatibility with future devices, these bits must be set to zero when tccr1a is written when operating in a p w m mode. w hen writing a logical one to the foc1a/foc1b bit, an immediate compare match is forced on the w aveform generation unit. the oc1a/oc1b output is changed according to its com1x[1:0] bits setting. note that the foc1a/foc1b bits are implemented as strobes. therefore it is the value present in the com1x[1:0] bits that determine the effect of the forced compare. table 15-6. clock select bit description cs12 cs11 cs10 description 0 0 0 no clock source (timer/counter stopped). 001clk i/o /1 (no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t1 pin. clock on falling edge. 1 1 1 external clock source on t1 pin. clock on rising edge. bit 7654 3210 (0x82) foc1a foc1b ? ? ? ? ? ? tccr1c read/ w rite r/ w r/ w rrrrrr initial value 0 0 0 0 0 0 0 0 134 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 a foc1a/foc1b strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (ctc) mode using ocr1a as top. the foc1a/foc1b bits are always read as zero. 15.11.4 tcnt1h and tcnt1l ? timer/counter1 the two timer/counter i/o locations (tcnt1h and tcnt1l , combined tcnt1) give direct access, both for read and for write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is perfo rmed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 111. modifying the counter (tcnt1) while the counte r is running introduces a risk of missing a com- pare match between tcnt1 and one of the ocr1x registers. w riting to the tcnt1 register blocks (removes) the compare match on the following timer clock for all compare units. 15.11.5 ocr1ah and ocr1al ? ou tput compare register 1 a 15.11.6 ocr1bh and ocr1bl ? ou tput compare register 1 b the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt1). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc1x pin. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the cp u writes to these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 111. bit 76543210 (0x85) tcnt1[15:8] tcnt1h (0x84) tcnt1[7:0] tcnt1l read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x89) ocr1a[15:8] ocr1ah (0x88) ocr1a[7:0] ocr1al read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x8b) ocr1b[15:8] ocr1bh (0x8a) ocr1b[7:0] ocr1bl read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 135 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 15.11.7 icr1h and icr1l ? input capture register 1 the input capture is updated with the counter (tcnt1) value each time an event occurs on the icp1 pin (or optionally on the analog comparator output for timer/counter1). the input capture can be used for defining the counter top value. the input capture register is 16-bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these regi sters, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 111. 15.11.8 timsk1 ? timer/counter 1 interrupt mask register ? bit 5 ? icie1: timer/counter1, input capture interrupt enable w hen this bit is written to one, and the i-flag in t he status register is set (interrupts globally enabled), the timer/counter1 input capture interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 55. ) is executed when the icf1 flag, located in tifr1, is set. ? bit 2 ? ocie1b: timer/counter1, output compare b match interrupt enable w hen this bit is written to one, and the i-flag in t he status register is set (interrupts globally enabled), the timer/counter1 output compare b match interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 55. ) is executed when the ocf1b flag, located in tifr1, is set. ? bit 1 ? ocie1a: timer/counter1, output compare a match interrupt enable w hen this bit is written to one, and the i-flag in t he status register is set (interrupts globally enabled), the timer/counter1 output compare a match interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 55. ) is executed when the ocf1a flag, located in tifr1, is set. ? bit 0 ? toie1: timer/counter1, overflow interrupt enable w hen this bit is written to one, and the i-flag in t he status register is set (interrupts globally enabled), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 55. ) is executed when the tov1 flag, located in tifr1, is set. bit 76543210 (0x87) icr1[15:8] icr1h (0x86) icr1[7:0] icr1l read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x6f) ? ?icie1 ? ? ocie1b ocie1a toie1 timsk1 read/ w rite r r r/ w rrr/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 136 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 15.11.9 tifr1 ? timer/counter1 interrupt flag register ? bit 5 ? icf1: timer/count er1, input capture flag this flag is set when a capture event occurs on the icp1 pin. w hen the input capture register (icr1) is set by the w gm1[3:0] to be used as the top value, the icf1 flag is set when the counter reaches the top value. icf1 is automatically cleared when the input capt ure interrupt vector is executed. alternatively, icf1 can be cleared by writing a logic one to its bit location. ? bit 2 ? ocf1b: timer/counter1, output compare b match flag this flag is set in the timer clock cycle afte r the counter (tcnt1) value matches the output compare register b (ocr1b). note that a forced output compare (foc 1b) strobe will not set the ocf1b flag. ocf1b is automatically cleared when the output compare match b interrupt vector is exe- cuted. alternatively, ocf1b can be cleared by writing a logic one to its bit location. ? bit 1 ? ocf1a: timer/counter1, output compare a match flag this flag is set in the timer clock cycle afte r the counter (tcnt1) value matches the output compare register a (ocr1a). note that a forced output compare (foc 1a) strobe will not set the ocf1a flag. ocf1a is automatically cleared when the output compare match a interrupt vector is exe- cuted. alternatively, ocf1a can be cleared by writing a logic one to its bit location. ? bit 0 ? tov1: timer/counter1, overflow flag the setting of this flag is dependent of the w gm1[3:0] bits setting. in normal and ctc modes, the tov1 flag is set when the timer overflows. refer to table 15-5 on page 132 for the tov1 flag behavior when using another w gm1[3:0] bits setting. tov1 is automatically cleared when the timer/c ounter1 overflow interrupt vector is executed. alternatively, tov1 can be cleared by writing a logic one to its bit location. bit 76543210 0x16 (0x36) ? ?icf1 ? ? ocf1b ocf1a tov1 tifr1 read/ w rite r r r/ w rrr/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 137 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 16. timer/counter0 and ti mer/counter1 prescalers timer/counter1 and timer/counter0 share the same prescaler module, but the timer/counters can have different prescaler settings. the description below applies to both timer/counter1 and timer/counter0. 16.1 prescaler reset the prescaler is free running, i.e., operates independently of the clock select logic of the timer/counter, and it is shared by timer/counter1 and timer/counter0. since the prescaler is not affected by the timer/counter? s clock select, the state of t he prescaler will have implications for situations where a prescaled clock is used. one example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > csn2:0 > 1). the number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to n+1 system clock cycles, where n equals the prescaler divisor (8, 64, 256, or 1024). it is possible to use the prescaler reset for synchronizing the timer/counter to program execu- tion. however, care must be taken if the other timer/counter that shares the same prescaler also uses prescaling. a prescaler reset will affect the prescaler period for all timer/coun ters it is connected to. 16.2 internal clock source the timer/counter can be clocked directly by the system clock (by setting the csn2:0 = 1). this provides the fastest operation, with a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the prescaler can be used as a clock source. the prescaled clock has a frequency of either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. 16.3 external clock source an external clock source applied to the t1/t0 pin can be used as timer/counter clock (clk t1 /clk t0 ). the t1/t0 pin is sampled once every system clock cycle by the pin synchronization logic. the synchronized (sampled) signal is then passed through the edge detector. figure 16-1 on page 137 shows a functional equivalent block diagram of the t1/t0 synchronization and edge detector logic. the registers are clocked at the positive edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk t1 /clk t 0 pulse for each positive (csn2:0 = 7) or negative (csn2:0 = 6) edge it detects. figure 16-1. t1/t0 pin sampling the synchronization and e dge detector logic introduces a de lay of 2.5 to 3.5 system clock cycles from an edge has been applied to the t1/t0 pin to the counter is updated. enabling and disabling of the clock input must be done when t1/t0 has been stable for at least one system clock cycle, otherwise it is a risk t hat a false timer/counter clock pulse is generated. tn_sync (to clock s elect logic) edge detector s ynchronization dq dq le dq tn clk i/o 138 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 each half period of the external clock applie d must be longer than one system clock cycle to ensure correct sampling. the external clock must be guaranteed to have less than half the sys- tem clock frequency (f extclk < f clk_i/o /2) given a 50/50% duty cycle. since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling fre- quency (nyquist sampling theorem). however, due to variation of the system clock frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f clk_i/o /2.5. an external clock source can not be prescaled. figure 16-2. prescaler for timer/counter0 and timer/counter1 (1) note: 1. the synchronization logic on the input pins ( t1/t0) is shown in figure 16-1 . p s r10 clear clk t1 clk t0 t1 t0 clk i/o s ynchronization s ynchronization 139 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 16.4 register description 16.4.1 gtccr ? general timer/counter control register ? bit 7 ? tsm: timer/counter synchronization mode w riting the tsm bit to one activates the timer/counter synchronization mode. in this mode, the value that is written to the psr2 and psr10 bits is kept, hence keeping the corresponding pres- caler reset signals asserted. this ensures that the corresponding timer/counters are halted and can be configured to the same value without the risk of one of them advancing during configura- tion. w hen the tsm bit is written to zero, the ps r2 and psr10 bits are cleared by hardware, and the timer/counters start counting simultaneously. ? bit 0 ? psr10: prescaler reset timer/counter1 and timer/counter0 w hen this bit is one, timer/count er1 and timer/counter0 prescaler will be reset. this bit is nor- mally cleared immediately by hardware, except if the tsm bit is set. note that timer/counter1 and timer/counter0 share the same prescaler and a reset of this prescaler will affect both timers. bit 7 6 5 4 3 2 1 0 0x23 (0x43) tsm ? ? ? ? ? psr2 psr10 gtccr read/ w rite r/ w rrrrrr/ w r/ w initial value 0 0 0 0 0 0 0 0 140 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 17. 8-bit timer/counter2 with pwm and asynchronous operation 17.1 features ? single compare unit counter ? clear timer on compare match (auto reload) ? glitch-free, phase correct pu lse width modulator (pwm) ? frequency generator ? 10-bit clock prescaler ? overflow and compare match inte rrupt sources (tov2 and ocf2a) ? allows clocking from external 32khz watch crystal independent of the i/o clock 17.2 overview a simplified block diagram of the 8-bit timer/counter is shown in figure 17-1 . for the actual placement of i/o pins, refer to ?pin configurations? on page 2 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit loca- tions are listed in the ?register description? on page 154 . figure 17-1. 8-bit timer/counter block diagram 17.2.1 registers the timer/counter (tcnt2) and output compare register (ocr2a) are 8-bit registers. inter- rupt request (shorten as int.req.) signals are al l visible in the timer interrupt flag register (tifr2). all interrupts are individually masked with the timer interrupt mask register (timsk2). tifr2 and timsk2 are not shown in the figure. timer/counter data b u s = tcntn waveform generation ocnx = 0 control logic = 0xff top bottom count clear direction tovn (int.req.) ocnx (int.req.) synchronization unit ocrnx tccrnx assrn s tatus flags clk i/o clk asy s ynchronized s tatus flags asynchronous mode select (a s n) tosc1 t/c oscillator tosc2 prescaler clk tn clk i/o 141 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 the timer/counter can be clocked internally, via the prescaler, or asynchronously clocked from the tosc1/2 pins, as detailed later in this section. the asynchronous operation is controlled by the asynchronous status regist er (assr). the clock select lo gic block controls which clock source the timer/counter uses to increment (or de crement) its value. the timer/counter is inac- tive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t2 ). the double buffered output compare register (ocr2a) is compared with the timer/counter value at all times. the result of the compare can be used by the w aveform generator to gener- ate a p w m or variable frequency output on the output compare pin (oc2a). see ?output compare unit? on page 142. for details. the compare match event will also set the compare flag (ocf2a) which can be used to generate an output compare interrupt request. 17.2.2 definitions many register and bit references in this document are written in general form. a lower case ?n? replaces the timer/counter number, in this case 2. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt2 for accessing timer/counter2 counter value and so on. the definitions in table 17-1 are also used extensively throughout the section. 17.3 timer/counter clock sources the timer/counter can be clocked by an internal synchronous or an external asynchronous clock source. the clock source clk t2 is by default equal to the mcu clock, clk i/o . w hen the as2 bit in the assr register is written to logic one, the clock source is taken from the timer/counter oscillator connected to tosc1 and tosc2. fo r details on asynchronous operation, see ?assr ? asynchronous status register? on page 157 . for details on clock sour ces and prescaler, see ?timer/counter prescaler? on page 153 . 17.4 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 17-2 shows a block diagram of the counter and its surrounding environment. figure 17-2. counter unit block diagram table 17-1. timer/counter definitions bottom the counter reaches the bottom when it becomes zero (0x00). max the counter reaches its maximum wh en it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr2a register. the assignment is dependent on the mode of operation. data b u s tcntn control logic count tovn (int.req.) top bottom direction clear tosc1 t/c oscillator tosc2 prescaler clk i/o clk tn 142 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 signal description (internal signals): count increment or decrement tcnt2 by 1. direction selects between increment and decrement. clear clear tcnt2 (set all bits to zero). clk t 2 timer/counter clock. top signalizes that tcnt2 has reached maximum value. bottom signalizes that tcnt2 has reached minimum value (zero). depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t2 ). clk t2 can be generated from an external or internal clock source, selected by the clock select bits (cs2[2:0]). w hen no clock source is selected (cs2[2:0] = 0) the timer is stopped. however, the tcnt2 value can be accessed by the cpu, regardless of whether clk t2 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the w gm21 and w gm20 bits located in the timer/counter control register (tccr2a). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare output oc2a. for more details about advanced count ing sequences and waveform generation, see ?modes of operation? on page 145 . the timer/counter overflow flag (tov2) is set according to the mode of operation selected by the w gm2[1:0] bits. tov2 can be used for generating a cpu interrupt. 17.5 output compare unit the 8-bit comparator continuously compares tcnt2 with the output compare register (ocr2a). w henever tcnt2 equals ocr2a, the comparator signals a match. a match will set the output compare flag (ocf2a) at the next timer clock cycle. if enabled (ocie2a = 1), the output compare flag generates an output compare interrupt. the ocf2a flag is automatically cleared when the interrupt is executed. alternat ively, the ocf2a flag can be cleared by soft- ware by writing a logical one to its i/o bit location. the w aveform generator uses the match signal to generate an output according to operating mode set by the w gm2[1:0] bits and com- pare output mode (com2a[1:0]) bits. the max and bottom signals are used by the w aveform generator for handling the special cases of the extreme values in some modes of operation ( ?modes of operation? on page 145 ). figure 17-3 shows a block diagram of the output compare unit. 143 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 17-3. output compare unit, block diagram the ocr2a register is double buffered when using any of the pulse w idth modulation (p w m) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocr2a compare register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical p w m pulses, thereby making the output glitch-free. the ocr2a register access may seem complex, but this is not case. w hen the double buffer- ing is enabled, the cpu has access to the ocr2 a buffer register, and if double buffering is disabled the cpu will access the ocr2a directly. 17.5.1 force output compare in non-p w m waveform generation modes, the match output of the comparator can be forced by writing a one to the fo rce output compare (foc2a) bit. fo rcing compare match will not set the ocf2a flag or reload/clear the ti mer, but the oc2a pin will be updated as if a real compare match had occurred (the com2a[1:0] bits setti ngs define whether the oc2a pin is set, cleared or toggled). 17.5.2 compare match bloc king by tcnt2 write all cpu write operations to the tcnt2 register will block any compare matc h that occurs in the next timer clock cycle, even when the timer is stopped. this feature allo ws ocr2a to be initial- ized to the same value as tcnt2 without triggering an interrupt when the timer/counter clock is enabled. 17.5.3 using the output compare unit since writing tcnt2 in any mode of operation will block all comp are matches for one timer clock cycle, there are risks involved when changing tcnt2 when using the output compare unit, independently of whether the timer/counter is running or not. if the value written to tcnt2 equals the ocr2a value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write the tcnt2 value equal to bottom when the counter is down counting. ocfn x (int.req.) = ( 8 -bit comparator ) ocrnx ocnx data b u s tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 144 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 the setup of the oc2a should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc2a value is to use the force output com- pare (foc2a) strobe bit in normal mode. the oc2a register keeps its value even when changing between w aveform generation modes. be aware that the com2a[1:0] bits are not double buffered together with the compare value. changing the com2a[1:0] bits will take effect immediately. 17.6 compare match output unit the compare output mode (com2a[1:0]) bits have two functions. the w aveform generator uses the com2a[1:0] bits for defining the output compare (oc2a) state at the next compare match. also, the com2a[1:0] bits control the oc2a pin output source. figure 17-4 shows a sim- plified schematic of the logic affected by the com2a[1:0] bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control regis- ters (ddr and port) that are affected by the com2a[1:0] bits are shown. w hen referring to the oc2a state, the reference is for the internal oc2a register, not the oc2a pin. figure 17-4. compare match output unit, schematic the general i/o port function is overridden by the output compare (oc2a) from the w aveform generator if either of the com2a[1:0] bits are set. however, the oc2a pin direction (input or output) is still controlled by the data direction register (ddr) for the port pin. the data direc- tion register bit for the oc2a pin (ddr_oc2a) must be set as output before the oc2a value is visible on the pin. the port override function is independent of the w aveform generation mode. the design of the output compare pin logic allows initialization of the oc2a state before the output is enabled. note that some com2a[1:0] bits settings are reserved for certain modes of operation. see ?register description? on page 154. 17.6.1 compare output mode and waveform generation the w aveform generator uses the com2a[1:0] bits differently in normal, ctc, and p w m modes. for all modes, setting the com2a[1:0] = 0 tells the w aveform generator that no action port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data b u s focnx clk i/o 145 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 on the oc2a register is to be performed on the next compare match. for compare output actions in the non-p w m modes refer to table 17-3 on page 155 . for fast p w m mode, refer to table 17-4 on page 155 , and for phase correct p w m refer to table 17-5 on page 155 . a change of the com2a[1:0] bits state will have effect at the first compare match after the bits are written. for non-p w m modes, the action can be forced to have immediate effect by using the foc2a strobe bits. 17.7 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the w aveform generation mode ( w gm2[1:0]) and compare out- put mode (com2a[1:0]) bits. the compare output mode bits do not affect the counting sequence, while the w aveform generation mode bits do. the com2a[1:0] bits control whether the p w m output generated should be inverted or not (inverted or non-inverted p w m). for non- p w m modes the com2a[1:0] bits control whether the output should be set, cleared, or toggled at a compare match ( see ?compare match output unit? on page 144. ). for detailed timing information refer to ?timer/counter timing diagrams? on page 149 . 17.7.1 normal mode the simplest mode of operation is the normal mode ( w gm2[1:0] = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 8-bit value (top = 0xff) and then restarts from the bot- tom (0x00). in normal o peration the timer/counter overflow flag (tov2) will be set in the same timer clock cycle as the tcnt2 becomes zero. the tov2 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov2 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the out- put compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 17.7.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode ( w gm[1:0] = 2), the ocr2a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt2) matches the ocr2a. the ocr2a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 17-5 . the counter value (tcnt2) increases until a compare match occurs between tcnt2 and ocr2a, and then counter (tcnt2) is cleared. 146 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 17-5. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocf2a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing the top to a value close to bottom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr2a is lower than the cur- rent value of tcnt2, the c ounter will miss the compare matc h. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the oc2a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com2a[1:0] = 1). the oc2a value will not be visible on the port pin unless the data direction for the pin is set to output. the waveform generated will have a maximum frequency of f oc2a =f clk_i/o /2 when ocr2a is set to zero (0x00). the waveform frequency is defined by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). as for the normal mode of operation, the tov2 flag is set in the same timer clock cycle that the counter counts from max to 0x00. 17.7.3 fast pwm mode the fast pulse w idth modulation or fast p w m mode ( w gm2[1:0] = 3) provides a high frequency p w m waveform generation option. the fast p w m differs from the other p w m option by its sin- gle-slope operation. the counter counts from bottom to max then restarts from bottom. in non-inverting compare output mode, the output compare (oc2a) is cleared on the compare match between tcnt2 and ocr2a, and set at bottom. in inverting compare output mode, the output is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast p w m mode can be twice as high as the phase correct p w m mode that uses dual-slope operation. this high frequency makes the fast p w m mode well suited for power regulation, rectification, and dac app lications. high frequency a llows physically small sized external components (coils, capacitors), and therefore reduces total system cost. in fast p w m mode, the counter is incremented until the counter value matches the max value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast p w m mode is shown in figure 17-6 . the tcnt2 value is in the timing diagram shown as a his- togram for illustrating the single-slope operation. the diagram includes non-inverted and tcntn ocnx (toggle) ocnx interrupt flag s et 1 4 period 2 3 (comnx1:0 = 1) f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------- - = 147 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 inverted p w m outputs. the small horizontal line marks on the tcnt2 slopes represent compare matches between ocr2a and tcnt2. figure 17-6. fast p w m mode, timing diagram the timer/counter overflow flag (tov2) is set each time the counter reaches max. if the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. in fast p w m mode, the compare unit allows generation of p w m waveforms on the oc2a pin. setting the com2a[1:0] bits to two will produce a non-inverted p w m and an inverted p w m out- put can be generated by setting the com2a[1:0] to three (see table 17-4 on page 155 ). the actual oc2a value will only be visi ble on the port pin if the data direction for the port pin is set as output. the p w m waveform is generated by setting (or clearing) the oc2a register at the com- pare match between ocr2a and tcnt2, and cleari ng (or setting) the oc2a register at the timer clock cycle the counter is cleared (changes from max to bottom). the p w m frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a p w m waveform output in the fast p w m mode. if the ocr2a is set equal to bottom, the output will be a narrow spike for each max+1 timer clock cycle. setting the ocr2a equal to max will result in a constantly high or low output (depending on the polarity of the output set by the com2a[1:0] bits.) a frequency (with 50% duty cycle) waveform output in fast p w m mode can be achieved by set- ting oc2a to toggle its logical level on each compare match (com2a[1:0[ = 1). the waveform generated will have a ma ximum frequency of f oc2 = f clk_i/o /2 when ocr2a is set to zero. this fea- ture is similar to the oc2a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast p w m mode. 17.7.4 phase correct pwm mode the phase correct p w m mode ( w gm2[1:0] = 1) provides a high resolution phase correct p w m waveform generation option. the phase correct p w m mode is based on a dual-slope operation. tcntn ocrnx update and tovn interrupt flag s et 1 period 2 3 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3 ) ocrnx interrupt flag s et 4 5 6 7 f ocnxpwm f clk_i/o n 256 ? ------------------ = 148 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 the counter counts repeatedly from bottom to max and then from max to bottom. in non- inverting compare output mode, the output compare (oc2a) is cleared on the compare match between tcnt2 and ocr2a while upcounting, and set on the compare match while down- counting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the sym- metric feature of the dual-slope p w m modes, these modes are preferred for motor control applications. the p w m resolution for the phase correct p w m mode is fixed to eight bits. in phase correct p w m mode the counter is incremented until the counter value matches max. w hen the counter reaches max, it changes the count direction. the tcnt2 value will be equal to max for one timer clock cycle. the timing diagram for the phase correct p w m mode is shown on figure 17-7 . the tcnt2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and inverted p w m outputs. the small horizontal line marks on the tcnt2 slopes represent compare matches between ocr2a and tcnt2. figure 17-7. phase correct p w m mode, timing diagram the timer/counter overflow flag (tov2) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct p w m mode, the compare unit allows generation of p w m waveforms on the oc2a pin. setting the com2a[1:0] bits to two will produce a non-inverted p w m. an inverted p w m output can be generated by setting the com2a[1:0] to three (see table 17-5 on page 155 ). the actual oc2a value will only be visible on the port pin if the data direction for the port pin is set as output. the p w m waveform is generated by clearing (or setting) the oc2a register at the compare match between ocr2a and tcnt2 when the counter increments, and setting (or clearing) the oc2a register at compare match between ocr2a and tcnt2 when the coun- ter decrements. the p w m frequency for the output when using phase correct p w m can be calculated by the following equation: tovn interrupt flag s et ocnx interrupt flag s et 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3 ) ocrnx update f ocnxpcpwm f clk_i/o n 510 ? ------------------ = 149 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a p w m waveform output in the phase correct p w m mode. if the ocr2a is set equal to bottom, the output will be continuously low an d if set equal to max the output will be continuously high for non-inverted p w m mode. for inverted p w m the output will have th e opposite logic values. at the very start of period 2 in figure 17-7 ocn has a transition from high to low even though there is no compare match. the point of this transition is to guarantee symmetry around bot- tom. there are two cases that give a transition without compare match. ? ocr2a changes its value from max, like in figure 17-7 . w hen the ocr2a value is max the ocn pin value is the same as the result of a down-counting compare match. to ensure symmetry around bottom the ocn value at max must correspond to the result of an up- counting compare match. ? the timer starts counting from a value higher than the one in ocr2a, and for that reason misses the compare match and hence the ocn change that would have happened on the way up. 17.8 timer/counter timing diagrams the following figures show the timer/counter in synchronous mode, and the timer clock (clk t2 ) is therefore shown as a clock enable signal. in asynchronous mode, clk i/o should be replaced by the timer/counter oscillator clock. the figures include information on when interrupt flags are set. figure 17-8 contains timing data for basic timer/ counter operation. the figure shows the count sequence close to the max value in all modes other than phase correct p w m mode. figure 17-8. timer/counter timing diagram, no prescaling figure 17-9 shows the same timing data, but with the prescaler enabled. clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 150 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 17-9. timer/counter timing dia gram, with prescaler (f clk_i/o /8) figure 17-10 shows the setting of ocf2a in all modes except ctc mode. figure 17-10. timer/counter timing diagram, setting of ocf2a, with prescaler (f clk_i/o /8) figure 17-11 shows the setting of ocf2a and the clearing of tcnt2 in ctc mode. figure 17-11. timer/counter timing diagram, clear timer on compare match mode, with pres- caler (f clk_i/o /8) tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o / 8 ) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o / 8 ) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o / 8 ) 151 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 17.9 asynchronous operation of the timer/counter 17.9.1 asynchronous operation of timer/counter2 w hen timer/counter2 operates asynchronously, some considerations must be taken. ? w arning: w hen switching between asynchronous and synchronous clocking of timer/counter2, the timer registers tcnt2, ocr2a, and tccr2a might be corrupted. a safe procedure for switching clock source is: a. disable the timer/counter2 interrupts by clearing ocie2a and toie2. b. select clock source by setting as2 as appropriate. c. w rite new values to tcnt2, ocr2a, and tccr2a. d. to switch to asynchronous operation: w ait for tcn2ub, ocr2ub, and tcr2ub. e. clear the timer/counter2 interrupt flags. f. enable interrupts, if needed. ? the cpu main clock frequency must be more than four times th e oscillator frequency. ? w hen writing to one of the registers tcnt2, ocr2a, or tccr2a, the value is transferred to a temporary register, and latched after two positive edges on tosc1. the user should not write a new value before the contents of the temporary register have been transferred to its destination. each of the three mentioned registers have their individual temporary register, which means that e.g. writing to tcnt2 does not disturb an ocr2a write in progress. to detect that a transfer to the destination register has taken place, the asynchronous status register ? assr has been implemented. ? w hen entering power-save or adc noise reduction mode after having written to tcnt2, ocr2a, or tccr2a, the user must wait until the writte n register has been updated if timer/counter2 is used to wake up the device. otherwise, the mcu will enter sleep mode before the changes are effective. this is particularly important if the output compare2 interrupt is used to wake up the device, since the output compare function is disabled during writing to ocr2a or tcnt2. if the write cycle is not finished, and the mcu enters sleep mode before the ocr2ub bit returns to zero, the device will ne ver receive a compare match interrupt, and the mcu will not wake up. ? if timer/counter2 is used to wake the device up from power-save or adc noise reduction mode, precautions must be taken if the user wants to re-enter one of these modes: the interrupt logic needs one tosc1 cycle to be reset. if the time between wake-up and re- entering sleep mode is less than one tosc1 cycle, the interrupt will not occur, and the device will fail to wake up. if the user is in doubt whet her the time before re-entering power-save or adc noise reduction mode is sufficient, the following algorithm can be used to ensure that one tosc1 cycle has elapsed: a. w rite a value to tccr2a, tcnt2, or ocr2a. b. w ait until the corresponding update busy flag in assr returns to zero. c. enter power-save or adc noise reduction mode. ? w hen the asynchronous operation is selected, the 32.768khz osc illator for timer/counter2 is always running, except in power-down and standby modes. after a power-up reset or wake- up from power-down or standby mode, the user should be aware of the fact that this oscillator might take as long as one sec ond to stabilize. the us er is advised to wait for at least one second before using timer/counter2 after power-up or wake-up from power-down or standby mode. the contents of all timer/counter2 registers must be considered lost after a wake-up from power-down or standby mode due to unstable clock signal upon start-up, no matter whether the oscillator is in use or a cl ock signal is applied to the tosc1 pin. 152 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 ? description of wake up from power-save or adc noise reduction mode when the timer is clocked asynchronously: w hen the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. after wake-up, the mcu is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following sleep. ? reading of the tcnt2 register shortly after wake-up from power-save may give an incorrect result. since tcnt2 is clocked on the asynchronous tosc clock, reading tcnt2 must be done through a register synchronized to the internal i/o clock domain. synchronization takes place for every rising tosc1 edge. w hen waking up from power-save mode, and the i/o clock (clk i/o ) again becomes active, tcnt2 will read as th e previous value (bef ore entering sleep) until the next rising tosc1 edge. the phase of the tosc clock after waking up from power- save mode is essentially unpredictable, as it depends on the wake-up time. the recommended procedure for reading tcnt2 is thus as follows: a. w rite any value to either of the registers ocr2a or tccr2a. b. w ait for the corresponding update busy flag to be cleared. c. read tcnt2. ? during asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes 3 processor cycles plus one timer cycle. the timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the interrupt flag. the output compare pin is changed on the timer clock and is not synchronized to the processor clock. 153 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 17.10 timer/counter prescaler figure 17-12. prescaler for timer/counter2 the clock source for timer/counter2 is named clk t2s . clk t2s is by default connected to the main system i/o clock clk i o . by setting the as2 bit in assr, timer/counter2 is asynchronously clocked from the tosc1 pin. this enables us e of timer/counter2 as a real time counter (rtc). w hen as2 is set, pins tosc1 and tosc2 are disconnected from port c. a crystal can then be connected between the tosc1 and tosc2 pins to serve as an independent clock source for timer/counter2 . the oscillator is optimized for use with a 32.768khz crystal. if apply- ing an external clock on tosc1, the exclk bit in assr must be set. for timer/counter2, the possible prescaled selections are: clk t2s /8, clk t2s /32, clk t2s /64, clk t2s /128, clk t2s /256, and clk t2s /1024. additionally, clk t2s as well as 0 (stop) may be selected. setting the psr2 bit in gtccr resets the prescaler. this allows the user to operate with a pre- dictable prescaler. 10-bit t/c pre s caler timer/counter2 clock s ource clk i/o clk t2 s to s c1 a s 2 c s 20 c s 21 c s 22 clk t2 s / 8 clk t2 s /64 clk t2 s /12 8 clk t2 s /1024 clk t2 s /256 clk t2 s / 3 2 0 p s r2 clear clk t2 154 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 17.11 register description 17.11.1 tccr2a ? timer/counter control register a ? bit 7 ? foc2a: force output compare a the foc2a bit is only active when the w gm bits specify a non-p w m mode. however, for ensur- ing compatibility with future devices, this bit mu st be set to zero when tccr2a is written when operating in p w m mode. w hen writing a logical one to the foc2a bit, an immediate compare match is forced on the w aveform generation unit. the oc2a output is changed according to its com2a[1:0] bits setting. note that the foc2a bit is implemented as a strobe. therefore it is the value present in the com2a[1:0] bits that determines the effect of the forced compare. a foc2a strobe will not gen erate any interrupt, nor will it cl ear the timer in ctc mode using ocr2a as top. the foc2a bit is always read as zero. ? bit 6, 3 ? wgm2[1:0]: waveform generation mode these bits control the counting sequence of the counter, the source for the maximum (top) counter value, and what type of waveform generation to be used. modes of operation supported by the timer/counter unit are: normal mode, clear timer on compare match (ctc) mode, and two types of pulse w idth modulation (p w m) modes. see table 17-2 and ?modes of operation? on page 145 . note: 1. the ctc2 and p w m2 bit definition names are now obsolete. use the w gm2[1:0] definitions. however, the functionality and location of these bits are compatible with previous versions of the timer. ? bit 5:4 ? com2a[1:0]: compare match output mode a these bits control the output compare pin (oc2a) behavior. if one or both of the com2a[1:0] bits are set, the oc2a output overrides the normal po rt functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to oc2a pin must be set in order to enable the output driver. w hen oc2a is connected to the pin, the f unction of the com2a1:0 bits depends on the w gm2[1:0] bit setting. table 17-3 shows the com2a1:0 bit functionality when the w gm2[1:0] bits are set to a normal or ctc mode (non-p w m). bit 76 5 4 3 210 (0xb0) foc2a wgm20 com2a1 com2a0 wgm21 cs22 cs21 cs20 tccr2a read/ w rite w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 table 17-2. w aveform generation mode bit description (1) mode wgm21 (ctc2) wgm20 (pwm2) timer/counter mode of operation top update of ocr2a at tov2 flag set on 0 0 0 normal 0xff immediate max 10 1p w m, phase correct 0xff top bottom 2 1 0 ctc ocr2a immediate max 31 1fast p w m0xffbottommax 155 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 table 17-4 shows the com2a[1:0] bit functionality when the w gm2[1:0] bits are set to fast p w m mode. note: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?fast p w m mode? on page 146 for more details. table 17-5 shows the com2a[1:0] bit functionality when the w gm2[1:0] bits are set to phase correct p w m mode. note: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct p w m mode? on page 147 for more details. table 17-3. compare output mode, non-p w m mode com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 0 1 toggle oc2a on compare match. 1 0 clear oc2a on compare match. 1 1 set oc2a on compare match. table 17-4. compare output mode, fast p w m mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 01reserved 10 clear oc2a on compare match, set oc2a at bottom (non-inverting mode). 11 set oc2a on compare match, clear oc2a at bottom (inverting mode). table 17-5. compare output mode, phase correct p w m mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 01reserved 10 clear oc2a on compare match when up-counting. set oc2a on compare match when down counting. 11 set oc2a on compare match when up-counting. clear oc2a on compare match when down counting. 156 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 ? bit 2:0 ? cs2[2:0]: clock select the three clock select bits select the clock source to be used by the timer/counter, see table 17-6 . 17.11.2 tcnt2 ? timer/counter register the timer/counter register gives direct ac cess, both for read and write operations, to the timer/counter unit 8-bit counter. w riting to the tcnt2 register blocks (removes) the compare match on the following timer clock. modifying the counter (tcnt2) while the counter is running, introduces a risk of missing a compare match between tcnt2 and the ocr2a register. 17.11.3 ocr2a ? output compare register a the output compare register a contains an 8-bi t value that is continuously compared with the counter value (tcnt2). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc2a pin. table 17-6. clock select bit description cs22 cs21 cs20 description 0 0 0 no clock source (timer/counter stopped). 001clk t2s /(no prescaling) 010clk t2s /8 (from prescaler) 011clk t2s /32 (from prescaler) 100clk t2s /64 (from prescaler) 101clk t2s /128 (from prescaler) 110clk t 2 s /256 (from prescaler) 111clk t 2 s /1024 (from prescaler) bit 76543210 (0xb2) tcnt2[7:0] tcnt2 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0xb3) ocr2a[7:0] ocr2a read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 157 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 17.11.4 timsk2 ? timer/counter2 interrupt mask register ? bit 1 ? ocie2a: timer/counter2 output compare match a interrupt enable w hen the ocie2a bit is written to one and the i-bit in the status register is set (one), the timer/counter2 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/coun ter2 occurs, i.e., when the ocf2a bit is set in the timer/coun- ter 2 interrupt flag register ? tifr2. ? bit 0 ? toie2: timer/counter2 overflow interrupt enable w hen the toie2 bit is written to one and the i-bit in the status register is set (one), the timer/counter2 overflow interrupt is enabled. the corresponding interrupt is executed if an overflow in timer/counter2 occurs, i.e., when the tov2 bit is set in the timer/counter2 interrupt flag register ? tifr2. 17.11.5 tifr2 ? timer/counter2 interrupt flag register ? bit 1 ? ocf2a: output compare flag 2 a the ocf2a bit is set (one) when a compare match occurs between the timer/counter2 and the data in ocr2a ? output compare register2. ocf2a is cleared by hardware when executing the corresponding interrupt handling vector. alter natively, ocf2a is cleared by writing a logic one to the flag. w hen the i-bit in sreg, ocie2a (timer/counter2 compare match interrupt enable), and ocf2a are set (one), the timer/counter2 compare match interrupt is executed. ? bit 0 ? tov2: timer/counter2 overflow flag the tov2 bit is set (one) when an overflow occu rs in timer/counter2. tov2 is cleared by hard- ware when executing the corresponding interrupt handling vector. alternatively, tov2 is cleared by writing a logic one to the flag. w hen the sreg i-bit, toie2a (timer/counter2 overflow inter- rupt enable), and tov2 are set (one), the timer/ counter2 overflow interrupt is executed. in p w m mode, this bit is set when timer/counter2 changes counting direction at 0x00. 17.11.6 assr ? asynchronous status register ? bit 4 ? exclk: enable external clock input w hen exclk is written to one, and asynchronous clock is selected, the external clock input buf- fer is enabled and an external cl ock can be input on timer oscilla tor 1 (tosc1) pin instead of a 32khz crystal. w riting to exclk should be done before asynchronous operation is selected. note that the crystal oscillator will only run when this bit is zero. bit 76543210 (0x70) ? ? ? ? ? ? ocie2a toie2 timsk2 read/ w rite rrrrrrr/ w r/ w initial value00000000 bit 76543210 0x17 (0x37) ? ? ? ? ? ? ocf2a tov2 tifr2 read/ w rite rrrrrrr/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 (0xb6) ? ? ? exclk as2 tcn2ub ocr2ub tcr2ub assr read/ w riterrrr/ w r/ w rrr initial value 0 0 0 0 0 0 0 0 158 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 ? bit 3 ? as2: asynchronous timer/counter2 w hen as2 is written to zero, timer/counter2 is clocked from the i/o clock, clk i/o . w hen as2 is written to one, timer/counter2 is clocked from a crystal oscilla tor connected to the timer oscil- lator 1 (tosc1) pin. w hen the value of as2 is changed, the contents of tcnt2, ocr2a, and tccr2a might be corrupted. ? bit 2 ? tcn2ub: timer/counter2 update busy w hen timer/counter2 operates asynchronously and tcnt2 is written, this bit becomes set. w hen tcnt2 has been updated from the temporary storage register, this bit is cleared by hard- ware. a logical zero in this bit indicates that tcnt2 is ready to be updated with a new value. ? bit 1 ? ocr2ub: output co mpare register2 update busy w hen timer/counter2 operates asynchronously and ocr2a is written, this bit becomes set. w hen ocr2a has been updated from the temporary storage register, this bit is cleared by hard- ware. a logical zero in this bit indicates that ocr2a is ready to be updated with a new value. ? bit 0 ? tcr2ub: timer/counter control register2 update busy w hen timer/counter2 operates asynchronously and tccr2a is written, this bit becomes set. w hen tccr2a has been updated from the temporary storage regi ster, this bit is cleared by hardware. a logical zero in this bit indicates that tccr2a is ready to be updated with a new value. if a write is performed to any of the three timer/counter2 registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. the mechanisms for reading tcnt2, ocr2a, and tccr2a are different. w hen reading tcnt2, the actual timer value is read. w hen reading ocr2a or tccr2 a, the value in the tem- porary storage register is read. 17.11.7 gtccr ? general time r/counter control register ? bit 1 ? psr2: prescaler reset timer/counter2 w hen this bit is one, the time r/counter2 prescaler will be rese t. this bit is normally cleared immediately by hardware. if the bit is written wh en timer/counter2 is operating in asynchronous mode, the bit will remain one until the presca ler has been reset. the bit will not be cleared by hardware if the tsm bit is set. refer to the description of the ?bit 7 ? tsm: timer/counter syn- chronization mode? on page 139 for a description of the timer/counter synchronization mode. bit 7 6 5 4 3 2 1 0 0x23 (0x43) tsm ? ? ? ? ? psr2 psr10 gtccr read/ w rite r/ w rrrrrr/ w r/ w initial value 0 0 0 0 0 0 0 0 159 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 18. spi ? serial peripheral interface 18.1 features ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? end of transmission interrupt flag ? write collision flag protection ? wake-up from idle mode ? double speed (ck/2) master spi mode 18.2 overview the serial peripheral interface (spi) allows hi gh-speed synchronous data transfer between the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p and peripheral devices or between several avr devices. the prspi bit in ?prr ? power reduction register? on page 45 must be written to zero to enable spi module. figure 18-1. spi block diagram (1) note: 1. refer to figure 1-1 on page 2 , and table 13-3 on page 76 for spi pin placement. the interconnection between master and slave cpus with spi is shown in figure 18-2 . the sys- tem consists of two shift registers, and a master clock generator. the spi master initiates the spi2x spi2x divider /2/4/ 8 /16/ 3 2/64/12 8 160 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 communication cycle when pu lling low the slave select ss pin of the desired slave. master and slave prepare the data to be sent in their respective shift registers, and the master generates the required clock pulses on the sck line to interchange data. data is always shifted from mas- ter to slave on the master out ? slave in, mosi, line, and from slave to master on the master in ? slave out, miso, line. after ea ch data packet, the master will synchronize the slave by pulling high the slave select, ss , line. w hen configured as a master, the spi interface has no automatic control of the ss line. this must be handled by user software before communication can start. w hen this is do ne, writing a byte to the spi data register starts the spi clock generator, and the hardware shifts the eight bits into the slave. after shifting one byte , the spi clock generator stops, setting the end of transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the master may continue to shift the next byte by writing it into spdr, or signal the end of packet by pulling high the slave select, ss line. the last incoming byte will be kept in the buffer register for later use. w hen configured as a slave, the spi interface will remain sleeping with miso tri-stated as long as the ss pin is driven high. in this state, software may update the contents of the spi data register, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been completely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr register is set, an interrupt is requested. the slave may continue to place new data to be sent into spdr before reading the incoming data. the last incoming byte will be kept in the buffer register for later use. figure 18-2. spi master-slave interconnection the system is single buffered in the transmit di rection and double buffered in the receive direc- tion. this means that bytes to be transmitted cannot be written to the spi data register before the entire shift cycle is completed. w hen receiving data, however, a received character must be read from the spi data register before the next character has been completely shifted in. oth- erwise, the first byte is lost. in spi slave mode, the control logic will sample the incoming signal of the sck pin. to ensure correct sampling of the clock signal, the minimum low and high periods should be: low period: longer than 2 cpu clock cycles high period: longer than 2 cpu clock cycles. w hen the spi is enabled, the data direction of the mosi, miso, sck, and ss pins is overridden according to table 18-1 . for more details on automatic port overrides, refer to ?alternate port functions? on page 74 . s hift enable 161 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 note: 1. see ?alternate functions of port b? on page 76 for a detailed description of how to define the direction of the user defined spi pins. the following code examples show how to initialize the spi as a master and how to perform a simple transmission. ddr_spi in the examples mu st be replaced by the actual data direction register controlling the spi pins. dd_mosi, dd_miso and dd_sck must be replaced by the actual data direction bits for these pins. e.g. if mosi is placed on pin pb5, replace dd_mosi with ddb5 and ddr_spi with ddrb. table 18-1. spi pin overrides (1) pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input 162 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 note: 1. ?about code examples? on page 9 assembly code example (1) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< 165 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 18.4 data modes there are four combinations of sck phase and polarity with respect to serial data, which are determined by control bits cpha and cpol. the spi data transfer formats are shown in figure 18-3 and figure 18-4 . data bits are shifted out and latched in on opposite edges of the sck sig- nal, ensuring sufficient time for data signals to st abilize. this is clearly seen by summarizing table 18-3 and table 18-4 , as done below: figure 18-3. spi transfer format with cpha = 0 figure 18-4. spi transfer format with cpha = 1 table 18-2. cpol functionality leading edge traili ng edge spi mode cpol=0, cpha=0 sample (rising) setup (falling) 0 cpol=0, cpha=1 setup (rising) sample (falling) 1 cpol=1, cpha=0 sample (falling) setup (rising) 2 cpol=1, cpha=1 setup (falling) sample (rising) 3 bit 1 bit 6 l s b m s b s ck (cpol = 0) mode 0 s ample i mo s i/mi s o change 0 mo s i pin change 0 mi s o pin s ck (cpol = 1) mode 2 ss m s b l s b bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 m s b first (dord = 0) l s b first (dord = 1) sck (cpol = 0) mode 1 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 3 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb fir s t (dord = 0) lsb fir s t (dord = 1) 166 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 18.5 register description 18.5.1 spcr ? spi control register ? bit 7 ? spie: spi interrupt enable this bit causes the spi in terrupt to be executed if spif bit in the spsr register is set and the if the global interrupt enable bit in sreg is set. ? bit 6 ? spe: spi enable w hen the spe bit is written to one, the spi is enabled. this bit must be set to enable any spi operations. ? bit 5 ? dord: data order w hen the dord bit is written to one, the lsb of the data word is transmitted first. w hen the dord bit is written to zero, the msb of the data word is transmitted first. ? bit 4 ? mstr: master/slave select this bit selects master spi mode when written to one, and slave spi mode when written logic zero. if ss is configured as an input and is driven low while mstr is set, mstr will be cleared, and spif in spsr will become set. the user will th en have to set mstr to re-enable spi mas- ter mode. ? bit 3 ? cpol: clock polarity w hen this bit is written to one, sck is high when idle. w hen cpol is written to zero, sck is low when idle. refer to figure 18-3 and figure 18-4 for an example. the cpol functionality is sum- marized below: ? bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determine if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 18-3 and figure 18-4 for an example. the cpol functionality is summarized below: ? bits 1, 0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the dev ice configured as a master. spr1 and spr0 have no effect on the slave. bit 76543210 0x2c (0x4c) spie spe dord mstr cpol cpha spr1 spr0 spcr read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 table 18-3. cpol functionality cpol leading edge trailing edge 0 rising falling 1 falling rising table 18-4. cpha functionality cpha leading edge trailing edge 0 sample setup 1 setup sample 167 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 the relationship between sck and the oscillator clock frequency f osc is shown in the following table: 18.5.2 spsr ? spi status register ? bit 7 ? spif: spi interrupt flag w hen a serial transfer is complete, the spif flag is set. an interrupt is generated if spie in spcr is set and global interrupts are enabled. if ss is an input and is dr iven low when the spi is in master mode, this will also set the spif flag. spif is cleared by hardwa re when executing the corresponding interrupt handling vector. alternatively, the spif bit is cleared by first reading the spi status register with spif set, then accessing the spi data register (spdr). ? bit 6 ? wcol: write collision flag the w col bit is set if the spi data register (s pdr) is written during a data transfer. the w col bit (and the spif bit) are cleared by first reading the spi status register with w col set, and then accessing the spi data register. ? bit 5:1 ? reserved these bits are reserved and will always read as zero. ? bit 0 ? spi2x: double spi speed bit w hen this bit is written logic one the spi s peed (sck frequency) will be doubled when the spi is in master mode (see table 18-5 ). this means that the mini mum sck period will be two cpu clock periods. w hen the spi is configured as slave, the spi is only guaranteed to work at f osc /4 or lower. the spi interface on the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p is also used for program memory and eeprom downloading or uploading. see page 298 for serial program- ming and verification. table 18-5. relationship between sck and the oscillator frequency spi2x spr1 spr0 sck frequency 000 f osc / 4 001 f osc / 16 010 f osc / 64 011 f osc / 128 100 f osc / 2 101 f osc / 8 110 f osc / 32 111 f osc / 64 bit 76543210 0x2d (0x4d) spif wcol ? ? ? ? ? spi2x spsr read/ w rite rrrrrrrr/ w initial value 0 0 0 0 0 0 0 0 168 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 18.5.3 spdr ? spi data register the spi data register is a read/write register used for data transfer between the register file and the spi shift register. w riting to the register initiates data transmission. reading the regis- ter causes the shift register receive buffer to be read. bit 76543210 0x2e (0x4e) msb lsb spdr read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial valuexxxxxxxxundefined 169 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 19. usart 19.1 features ? full duplex operation (independent se rial receive and transmit registers) ? asynchronous or synchronous operation ? master or slave clocked synchronous operation ? high resolution baud rate generator ? supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits ? odd or even parity generation and parity check supported by hardware ? data overrun detection ? framing error detection ? noise filtering includes false start bit detection and digital low pass filter ? three separate interrupts on tx complete, tx data register empty and rx complete ? multi-processor communication mode ? double speed asynchronous communication mode 19.2 overview the universal synchronous and asynchronous serial receiver and transmitter (usart) is a highly flexible serial communication device. the prusart0 bit in ?prr ? power reduction register? on page 45 must be written to zero to enable usart0 module. a simplified block diagram of the usart transmitter is shown in figure 19-1 on page 170 . cpu accessible i/o registers and i/o pins are shown in bold. 170 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 19-1. usart block diagram (1) note: 1. refer to figure 1-1 on page 2 and figure 13-5 on page 74 for usart pin placement. the dashed boxes in the block diagram separate the three main parts of the usart (listed from the top): clock generator, transmitter and receiver. control registers are shared by all units. the clock generation logic consis ts of synchronization logic fo r external clock input used by synchronous slave operation, and the baud rate generator. the xck (transfer clock) pin is only used by synchronous transfer mode. the transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame formats. the write buffer allows a continuous transfer of data without any delay between frames. the receiver is the most complex part of the usart module due to its clock and data recovery units. the recovery units are used for asynchronous data reception. in addition to the recovery units, the receiver includes a parity checker, control logic, a shift register and a two level receive buffer (udrn). the receiver supports the same frame formats as the transmitter, and can detect frame error, data overrun and parity errors. parity generator ubrr[h:l] udr (transmit) ucsra ucsrb ucsrc baud rate generator transmit shift register receive shift register rxd txd pin control udr (receive) pin control xck data recovery clock recovery pin control tx control rx control parity checker data bus osc sync logic clock generator transmitter receiver 171 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 19.2.1 avr usart vs. avr uart ? compatibility the usart is fully compatible with the avr uart regarding: ? bit locations inside all usart registers. ? baud rate generation. ? transmitter operation. ? transmit buffer functionality. ? receiver operation. however, the receive bu ffering has two improvements that will affect the comp atibility in some special cases: ? a second buffer register has been added. the two buffer registers operate as a circular fifo buffer. therefore the udrn must only be read once for each incoming data! more important is the fact that the error flags (fen and dorn) and the ninth data bit (rxb8n) are buffered with the data in the receive buffer. therefore the status bits must always be read before the udrn register is read. othe rwise the error status will be lost since the buffer state is lost. ? the receiver shift register can now act as a third buffer level. this is done by allowing the received data to remain in the serial shift register (see figure 19-1 ) if the buffer registers are full, until a new start bit is detected. the usart is therefore more resistant to data overrun (dorn) error conditions. the following control bits have changed name, but have same functionality and register location: ? chr9 is changed to ucszn2. ? or is changed to dorn. 19.3 clock generation the clock generation logic generates the base clock for the transmitter and receiver. the usart supports four modes of clock operati on: normal asynchronous, double speed asyn- chronous, master synchronous and slave synchronous mode. the umseln bit in usart control and status register c (ucsrnc) selects between asynchronous and synchronous operation. double speed (asynchronous mode only) is controlled by the u2xn found in the ucsrna register. w hen using synchronous mode (umseln = 1), the data direction register for the xck pin (ddr_xck) controls whether t he clock source is internal (master mode) or external (slave mode). the xck pin is only active when using synchronous mode. figure 19-2 shows a block diagram of the clock generation logic. figure 19-2. clock generation logic, block diagram prescaling down-counter /2 ubrr /4 /2 fosc ubrr+1 sync register osc xck pin txclk u2x umsel ddr_xck 0 1 0 1 xcki xcko ddr_xck rxclk 0 1 1 0 edge detector ucpol 172 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 signal description: txclk transmitter clock (internal signal). rxclk receiver base clock (internal signal). xcki input from xck pin (internal signal). used for synchronous slave operation. xcko clock output to xck pin (internal signal). used for synchronous master operation. fosc xtal pin frequency (system clock). 19.3.1 internal clock generation ? the baud rate generator internal clock generation is used for the as ynchronous and the synchronous master modes of operation. the description in this section refers to figure 19-2 . the usart baud rate register (ubrrn) and the down-counter connected to it function as a programmable prescaler or baud rate generator. the down-counter, running at system clock (f osc ), is loaded with the ubrrn value each time the counter has counted down to zero or when the ubrrln register is written. a clock is gene rated each time the counter reaches zero. this clock is the baud rate generator clock output (= f osc /(ubrrn+1)). the transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. the baud rate generator out- put is used directly by the receiver?s clock an d data recovery units. however, the recovery units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the umseln, u2xn and ddr_xck bits. table 19-1 contains equations for calculating the baud rate (in bits per second) and for calculat- ing the ubrrn value for each mode of operation using an internally generated clock source. note: 1. the baud rate is defined to be the transfer rate in bit per second (bps) baud baud rate (in bits per second, bps) f osc system oscillator clock frequency ubrrn contents of the ubrrhn and ubrrln registers, (0-4095) some examples of ubrrn values for some system clock frequencies are found in table 19-4 (see page 189 ). 19.3.2 double speed operation (u2xn) the transfer rate can be doubled by setting the u2xn bit in ucsrna. setting this bit only has effect for the asynchronous operation. set this bit to zero when using synchronous operation. table 19-1. equations for calculating baud rate register setting operating mode equation for calculating baud rate (1) equation for calculating ubrrn value asynchronous normal mode (u2xn = 0) asynchronous double speed mode (u2xn = 1) synchronous master mode baud f osc 16 ubrr n 1 + () ----------------------------------------- - = ubrr n f osc 16 baud ----------------------- - 1 ? = baud f osc 8 ubrr n 1 + () -------------------------------------- - = ubrr n f osc 8 baud -------------------- 1 ? = baud f osc 2 ubrr n 1 + () -------------------------------------- - = ubrr n f osc 2 baud -------------------- 1 ? = 173 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. note however that the receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. for the transmitter, there are no downsides. 19.3.3 external clock external clocking is used by the synchronous sl ave modes of operation. the description in this section refers to figure 19-2 for details. external clock input from the xck pin is sampled by a synchronization register to minimize the chance of meta-stability. the output from the synchronization register must then pass through an edge detector before it can be used by the transmitter and receiver. this process intro- duces a two cpu clock period delay and theref ore the maximum external xck clock frequency is limited by the following equation: note that f osc depends on the stability of the system clock source. it is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. 19.3.4 synchronous clock operation w hen synchronous mode is used (umseln = 1), the xck pin will be used as either clock input (slave) or clock output (master). the dependency between the clock edges and data sampling or data change is the same. the basic principle is that data input (on rxd) is sampled at the opposite xck clock edge of the edge the data output (txd) is changed. figure 19-3. synchronous mode xck timing. the ucpoln bit ucrsc selects which xck clock edge is used for data sampling and which is used for data change. as figure 19-3 shows, when ucpoln is zero the data will be changed at rising xck edge and sampled at falling xck edge. if ucpoln is se t, the data will be changed at falling xck edge and sampl ed at rising xck edge. f xck f osc 4 ----------- < rxd / txd xck rxd / txd xck ucpol = 0 ucpol = 1 sample sample 174 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 19.4 frame formats a serial frame is defined to be one character of da ta bits with synchronizat ion bits (start and stop bits), and optionally a parity bi t for error checking. the usart accepts all 30 combinations of the following as valid frame formats: ? 1 start bit ? 5, 6, 7, 8, or 9 data bits ? no, even or odd parity bit ? 1 or 2 stop bits a frame starts with the start bit followed by the least significant data bit. then the next data bits, up to a total of nine, are succeeding, ending with t he most significant bit. if enabled, the parity bit is inserted after the data bits, before the stop bits. w hen a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. figure 19-4 on page 174 illustrates the possible combinations of the frame formats. bits inside brackets are optional. figure 19-4. frame formats st start bit, always low. (n) data bits (0 to 8). p parity bit. can be odd or even. sp stop bit, always high. idle no transfers on the communication line (rxd or txd). an idle line must be high. the frame format used by th e usart is set by the ucszn2:0, upm1n:0 and usbsn bits in ucsrnb and ucsrnc. the receiver and transmitter use the same setting. note that changing the setting of any of these bits will corrupt a ll ongoing communication for both the receiver and transmitter. the usart character size (ucszn2:0) bits select the number of data bits in the frame. the usart parity mode (upm1n:0) bits enable and set the type of parity bit. the selection between one or two stop bits is done by the usart stop bit select (usbsn) bit. the re ceiver ignores the second stop bit. an fen (frame error fen) will therefore only be detected in the cases where the first stop bit is zero. 19.4.1 parity bit calculation the parity bit is calculated by do ing an exclusive-or of all the data bits. if odd parity is used, the result of the exclusive or is inverted. the re lation between the parity bit and data bits is as follows: 1 0 2 3 4 [5] [6] [7] [8] [p] st sp1 [sp2] (st / idle) (idle) frame p even d n 1 ? d 3 d 2 d 1 d 0 0 p odd d n 1 ? d 3 d 2 d 1 d 0 1 = = 175 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 p even parity bit using even parity p odd parity bit using odd parity d n data bit n of the character if used, the parity bit is located between the last data bit and first stop bit of a serial frame. 19.5 usart initialization the usart has to be initialized before any communication can take place. the initialization pro- cess normally consists of setting the baud rate, setting frame format and enabling the transmitter or the receiver depending on the usage. for interrupt driven usart operation, the global interrupt flag should be cleared (and interrupts globally disabled) when doing the initialization. before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. the txcn flag can be used to check that the transmitter has completed all transfers, and the rxcn flag can be used to check that there are no unread data in the receive buffer. note that the txcn flag must be cleared before each transmission (before udrn is written) if it is used for this purpose. the following simple usart initialization code examples show one assembly and one c func- tion that are equal in functionality. the exampl es assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. the baud rate is given as a function parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. 176 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 note: 1. see ?about code examples? on page 9. more advanced initialization routines can be made that include frame format as parameters, dis- able interrupts and so on. however, many appl ications use a fixed setting of the baud and control registers, and for these types of applicati ons the initialization code can be placed directly in the main routine, or be combined with initialization code for other i/o modules. assembly code example (1) usart_init: ; set baud rate sts ubrr0h, r17 sts ubrr0l, r16 ; enable receiver and transmitter ldi r16, (1< 180 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 19.7 data reception ? the usart receiver the usart receiver is enabled by writing th e receive enable (rxenn) bit in the ucsrnb register to one. w hen the receiver is enabled, the normal pin operation of the rxd pin is over- ridden by the usart and given the function as th e receiver?s serial input. the baud rate, mode of operation and frame format must be set up once before any serial reception can be done. if synchronous operation is used, the clock on the xck pin will be used as transfer clock. 19.7.1 receiving frames with 5 to 8 data bits the receiver starts data reception when it detects a valid start bit. each bit that follows the start bit will be sampled at the ba ud rate or xck clock, and shifted into the receive shift register until the first stop bit of a frame is received. a se cond stop bit will be ignored by the receiver. w hen the first stop bit is received, i.e., a complete serial frame is present in the receive shift register, the contents of the shift register will be moved into the receive buffer. the receive buffer can then be read by readin g the udrn i/o location. the following code example shows a simple us art receive function based on polling of the receive complete (rxcn) flag. w hen using frames with less than eight bits the most significant bits of the data read from the udrn will be masked to zero. th e usart has to be initialized before the function can be used. note: 1. see ?about code examples? on page 9. the function simply waits for data to be present in the receive buffer by checking the rxcn flag, before reading the buffer and returning the value. assembly code example (1) usart_receive: ; wait for data to be received sbis ucsr0a, rxc0 rjmp usart_receive ; get and return received data from buffer in r16, udr0 ret c code example (1) unsigned char usart_receive( void ) { /* wait for data to be received */ while ( !(ucsr0a & (1< 182 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 note: 1. ?about code examples? on page 9 the receive function example reads all the i/o r egisters into the register file before any com- putation is done. this gives an optimal receive buffer utilization since the bu ffer location read will be free to accept new data as early as possible. assembly code example (1) usart_receive: ; wait for data to be received sbis ucsr0a, rxc0 rjmp usart_receive ; get status and 9th bit, then data from buffer in r18, ucsr0a in r17, ucsr0b in r16, udr0 ; if error, return -1 andi r18,(1< 183 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 19.7.3 receive compete flag and interrupt the usart receiver has one flag that indicates the receiver state. the receive complete (rxcn) flag indicates if there are unread data present in the receive buf- fer. this flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled (rxenn = 0), the receive buffer will be flushed and cons equently the rxcn bit will become zero. w hen the receive complete interrupt enable (rxcien) in ucsrnb is set, the usart receive complete interrupt will be executed as long as the rxcn flag is se t (provided that global inter- rupts are enabled). w hen interrupt-driven data reception is used, the receive complete routine must read the received data from udrn in order to clear the rxcn flag, otherwise a new inter- rupt will occur once the inte rrupt routine terminates. 19.7.4 receiver error flags the usart receiver has three error flags: frame error (fen), data overrun (dorn) and parity error (upen). all can be accessed by reading ucsrna. common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. due to the buffering of the error flags, the ucsrna must be read before the receive buffer (udrn), since reading the udrn i/o location change s the buffer read location. another equality for the error flags is that they can not be altered by software doing a write to the flag location. however, all flags must be set to zero when the ucsrna is written for upward compatibility of future usart impl ementations. none of the error flags can genera te interrupts. the frame error (fen) flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. the fen flag is zero when the stop bit was correctly read (as one), and the fen flag will be one when the stop bit was incorrect (zero). this flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. the fen flag is not affected by the setting of the u sbsn bit in ucsrnc since the receiver ignores all, except for the first, stop bits. for compatibility with future devices, always set this bit to zero when writing to ucsrna. the data overrun (dorn) flag indicates data loss due to a receiver buffer full condition. a data overrun occurs when the receive buffer is full (two characters), it is a new character wait- ing in the receive shift register, and a new start bit is detected. if the dorn flag is set there was one or more serial frame lost between the frame last read from udrn, and the next frame read from udrn. for compatibility wi th future devices, always write this bit to zero when writing to ucsrna. the dorn flag is cleared when t he frame received was successfully moved from the shift register to the receive buffer. the parity error (upen) flag indicates that the next frame in the receive buffer had a parity error when received. if parity check is not enabled the upen bit will always be read zero. for compatibility with future devices, always set this bit to zero when writing to ucsrna. for more details see ?parity bit calculation? on page 174 and ?parity checker? on page 184 . 184 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 19.7.5 parity checker the parity checker is active when the high usart parity mode (upm1n) bit is set. type of par- ity check to be performed (odd or even) is selected by the upm0n bit. w hen enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. the result of the check is stored in the receive buffer together with the received data and stop bits. the parity error (upen) flag can then be read by software to check if the frame had a parity error. the upen bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (upm1n = 1). this bit is valid until the receive buffer (udrn) is read. 19.7.6 disabling the receiver in contrast to the transmitter, disabling of the receiver will be immediate. data from ongoing receptions will therefore be lost. w hen disabled (i.e ., the rxenn is set to zero) the receiver will no longer override the normal function of the rxd port pin. the receiver buffer fifo will be flushed when the receiver is disabled. remaining data in the buffer will be lost 19.7.7 flushing the receive buffer the receiver buffer fifo will be fl ushed when the receiver is disa bled, i.e., the buffer will be emptied of its contents. unread data will be lost. if the buffer has to be flushed during normal operation, due to for in stance an error conditi on, read the udrn i/o location until the rxcn flag is cleared. the following code example shows how to flush the receive buffer. note: 1. see ?about code examples? on page 9. assembly code example (1) usart_flush: sbis ucsr0a, rxc0 ret in r16, udr0 rjmp usart_flush c code example (1) void usart_flush( void ) { unsigned char dummy; while ( ucsr0a & (1< 186 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 19-6. sampling of data and parity bit the decision of the logic level of the received bit is taken by doing a majori ty voting of the logic value to the three samples in the center of the received bit. the center samples are emphasized on the figure by having the sample number inside boxes. the majority voting process is done as follows: if two or all three samples have high levels, the received bit is registered to be a logic 1. if two or all three samples have low levels, the received bit is registered to be a logic 0. this majority voting process acts as a low pass filter for the incoming signal on the rxd pin. the recovery process is then repeated until a complete frame is received. including the first stop bit. note that the receiver only uses the first stop bit of a frame. figure 19-7 on page 186 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. figure 19-7. stop bit sampling and ne xt start bit sampling the same majority voting is done to the stop bit as done for the other bits in the frame. if the stop bit is registered to have a logic 0 va lue, the frame error (fen) flag will be set. a new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. for normal speed mode, the first low level sample can be at point marked (a) in figure 19-7 on page 186 . for double speed mode the first low level must be delayed to (b). (c) marks a stop bit of full length. the early start bit detection influences the operational range of the receiver. 19.8.3 asynchronous operational range the operational range of the receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. if the transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the receiver does not have a similar (see table 19-2 on page 187 ) base frequency, the receiver will not be able to synchronize the frames to the start bit. the following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. 1234567 8 9 10 11 12 13 14 15 16 1 bit n 123 4 5 678 1 rxd sample (u2x = 0) sample (u2x = 1) 1234567 8 9 10 0/1 0/1 0/1 stop 1 123 4 5 6 0/1 rxd sample (u2x = 0) sample (u2x = 1) (a) (b) (c) r slow d 1 + () s s 1 ? ds ? s f ++ ------------------------------------------ - = r fast d 2 + () s d 1 + () ss m + ----------------------------------- = 187 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 d sum of character size and parity size (d = 5 to 10 bit) s samples per bit. s = 16 for normal speed mode and s = 8 for double speed mode. s f first sample number used for majority voting. s f = 8 for normal speed and s f = 4 for double speed mode. s m middle sample number used for majority voting. s m = 9 for normal speed and s m = 5 for double speed mode. r slow is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate. r fast is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate. table 19-2 and table 19-3 list the maximum receiver baud rate error that can be tolerated. note that normal speed mode has higher toleration of baud rate variations. the recommendations of the maximum receiver baud rate error was made under the assump- tion that the receiver and transmitter equally divides the maximum total error. there are two possible sources fo r the receivers baud rate erro r. the receiver?s system clock (xtal) will always have some minor instabilit y over the supply voltage range and the tempera- ture range. w hen using a crystal to generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. the second source for the error is more controllable. the baud rate generator can not always do an table 19-2. recommended maximum receiver baud rate error for normal speed mode (u2xn = 0) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 93.20 106.67 +6.67/-6.8 3.0 6 94.12 105.79 +5.79/-5.88 2.5 7 94.81 105.11 +5.11/-5.19 2.0 8 95.36 104.58 +4.58/-4.54 2.0 9 95.81 104.14 +4.14/-4.19 1.5 10 96.17 103.78 +3.78/-3.83 1.5 table 19-3. recommended maximum receiver baud rate error for double speed mode (u2xn = 1) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 94.12 105.66 +5.66/-5.88 2.5 6 94.92 104.92 +4.92/-5.08 2.0 7 95.52 104,35 +4.35/-4.48 1.5 8 96.00 103.90 +3.90/-4.00 1.5 9 96.39 103.53 +3.53/-3.61 1.5 10 96.70 103.23 +3.23/-3.30 1.0 188 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 exact division of the system frequency to get the baud rate wanted. in th is case an ubrrn value that gives an acceptable low error can be used if possible. 19.9 multi-processor communication mode setting the multi-processor communication m ode (mpcmn) bit in ucsrna enables a filtering function of incoming frames received by the usart receiver. frames that do not contain address information will be ignored and not put in to the receive buffer. this effectively reduces the number of incoming frames that has to be handled by the cpu, in a system with multiple mcus that communicate via the same serial bu s. the transmitter is unaffected by the mpcmn setting, but has to be used diffe rently when it is a part of a system utilizing the multi-processor communication mode. if the receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indi- cates if the frame contains data or address information. if the receiver is set up for frames with nine data bits, then the ninth bit (rxb8n) is used for identifying address and data frames. w hen the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. w hen the frame type bit is zero the frame is a data frame. the multi-processor communication mode enables several slave mcus to receive data from a master mcu. this is done by first decoding an address frame to find out which mcu has been addressed. if a particular slave mcu has been addressed, it will rece ive the following data frames as normal, while the other slave mcus will ignore the received frames until another address frame is received. 19.9.1 using mpcmn for an mcu to act as a master mcu, it can use a 9-bit character frame format (ucsz = 7). the ninth bit (txb8n) must be set when an address frame (txb8n = 1) or cleared when a data frame (txb = 0) is being transmitted. the slave mcus must in this case be set to use a 9-bit character frame format. the following procedure should be used to exchange data in multi-processor communication mode: 1. all slave mcus are in multi-processor communication mode (mpcmn in ucsrna is set). 2. the master mcu sends an address frame, and all slaves receive and read this frame. in the slave mcus, the rxcn flag in ucsrna will be set as normal. 3. each slave mcu reads the udrn register and determines if it has been selected. if so, it clears the mpcmn bit in ucsrna, otherwise it waits for the next address byte and keeps the mpcmn setting. 4. the addressed mcu will receive all data frames until a new address frame is received. the other slave mcus, which still have the mp cmn bit set, will ignore the data frames. 5. w hen the last data frame is received by the addressed mcu, the addressed mcu sets the mpcmn bit and waits for a new address frame from master. the process then repeats from 2. using any of the 5- to 8-bit character frame formats is possible, but impractical since the receiver must change between using n and n+1 character frame formats. this makes full- duplex operation difficult since the transmitter a nd receiver uses the same character size set- ting. if 5- to 8-bit character frames are used, the transmitter must be set to use two stop bit (usbsn = 1) since the first stop bit is used for indicating the frame type. do not use read-modify- w rite instructions (sbi and cbi) to set or clear the mpcmn bit. the mpcmn bit shares the same i/o location as the txcn flag and this might accidentally be cleared when using sbi or cbi instructions. 189 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 19.10 examples of ba ud rate setting for standard crystal and resonator frequencies, the most commonly used baud rates for asyn- chronous operation can be generated by using the ubrrn settings in table 19-4 . ubrrn values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table. higher error ratings are acceptable, but the re ceiver will have less noise resis- tance when the error ratings are high, especially for large serial frames (see ?asynchronous operational range? on page 186 ). the error values are calculat ed using the following equation: note: 1. ubrrn = 0, error = 0.0% error[%] baudrate closest match baudrate -------------------------------------------------------- 1 ? ?? ?? 100% ? = table 19-4. examples of ubrrn settings for co mmonly used oscillator frequencies baud rate (bps) f osc = 1.0000mhz f osc = 1.8432mhz f osc = 2.0000mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0. 0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8k ? ? 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5% 115.2k ? ? 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4k??????00.0%???? 250k??????????00.0% max. (1) 62.5 kbps 125 kbps 115.2 kbps 230.4 kbps 125 kbps 250 kbps 190 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 table 19-5. examples of ubrrn settings for common ly used oscillator frequencies (continued) baud rate (bps) f osc = 3.6864mhz f osc = 4.0000mhz f osc = 7.3728mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 230.0%470.0%250.2%510.2%470.0%950.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0% 28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0% 250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8% 0.5m ? ? 0 -7.8% ? ? 0 0.0% 0 -7.8% 1 -7.8% 1m ??????????0-7.8% max. (1) 230.4 kbps 460.8 kbps 250 kbps 0. 5 mbps 460.8 kbps 921.6 kbps 191 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 table 19-6. examples of ubrrn settings for common ly used oscillator frequencies (continued) baud rate (bps) f osc = 8.0000mhz f osc = 11.0592 mhz f osc = 14.7456mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.0% 28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0% 38.4k 12 0.2% 25 0.2% 17 0.0% 35 0.0% 23 0.0% 47 0.0% 57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0% 76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0% 115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0% 230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0% 250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3% 0.5m 0 0.0% 1 0.0% ? ? 2 -7.8% 1 -7.8% 3 -7.8% 1m ??00.0%????0-7.8%1-7.8% max. (1) 0.5 mbps 1 mbps 691.2 kbps 1.38 24 mbps 921.6 kbps 1.8432 mbps 1. ubrrn = 0, error = 0.0% 192 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 table 19-7. examples of ubrrn settings for common ly used oscillator frequencies (continued) baud rate (bps) f osc = 16.0000mhz f osc = 18.4320mhz f osc = 20.0000mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2% 28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2% 38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2% 57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9% 76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1.7% 32 -1.4% 115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4% 230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4% 250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0% 0.5m 1 0.0% 3 0.0% ? ? 4 -7.8% ? ? 4 0.0% 1m 00.0%10.0%???????? max. (1) 1 mbps 2 mbps 1.152 mbps 2.304 mbps 1.25 mbps 2.5 mbps 1. ubrrn = 0, error = 0.0% 193 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 19.11 register description 19.11.1 udrn ? usart i/o data register the usart transmit data buffer register and usart receive data buffer registers share the same i/o address re ferred to as usart data register or udrn. the transmit data buffer reg- ister (txb) will be the destination for data wri tten to the udrn register location. reading the udrn register location will retu rn the contents of the receiv e data buffer register (rxb). for 5-, 6-, or 7-bit char acters the upper unu sed bits will be ignored by the transmitter and set to zero by the receiver. the transmit buffer can only be written when the udren flag in the ucsrna register is set. data written to udrn wh en the udren flag is not set, will be ignored by the usart transmit- ter. w hen data is written to the transmit buffer, and the transmitter is enabled, the transmitter will load the data into the transmit shift regist er when the shift register is empty. then the data will be serially tr ansmitted on the txd pin. the receive buffer consists of a two level fifo . the fifo will change its state whenever the receive buffer is accessed. due to this behavior of the receive buffer, do not use read-modify- w rite instructions (sbi and cbi) on this location. be careful when using bit test instructions (sbic and sbis), since these also will change the state of the fifo. 19.11.2 ucsrna ? usart contro l and status register a ? bit 7 ? rxcn: usart receive complete n this flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread dat a). if the receiver is disabled, the receive buffer will be flushed and consequently the rxcn bit will become zero. the rxcn flag can be used to generate a receive complete interr upt (see description of the rxcien bit). ? bit 6 ? txcn: usart transmit complete n this flag bit is set when the entire frame in the transmit shift register has been shifted out and there are no new data currently present in the transmit buffer (udrn). the txc flag bit is auto- matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. the txc flag can generate a transmit complete interrupt (see descrip- tion of the txcie bit). ? bit 5 ? udren: usart data register empty n the udren flag indicates if the transmit buff er (udrn) is ready to receive new data. if udren is one, the buffer is empty, and therefore ready to be written. the udren flag can generate a data register empty interrupt (see description of the udrien bit). bit 76543210 (0xc6) rxb[7:0] udrn (read) txb[7:0] udrn (write) read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 bit 76543210 (0xc0) rxcn txcn udren fen dorn upen u2xn mpcmn ucsrna read/ w rite r r/ w rrrrr/ w r/ w initial value 0 0 1 0 0 0 0 0 194 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 udren is set after a reset to indicate that the transmitter is ready. ? bit 4 ? fen: frame error n this bit is set if the next character in the receive buffer had a frame error when received. i.e., when the first stop bit of the next character in the receive buffer is zero. this bit is valid until the receive buffer (udrn) is read. the fen bit is zero when the stop bit of received data is one. always set this bit to ze ro when writing to ucsrna. ? bit 3 ? dorn: data overrun n this bit is set if a data overrun condition is detected. a data overrun occurs when the receive buffer is full (two characters), it is a new char acter waiting in the receive shift register, and a new start bit is detected. this bi t is valid until the receive buffer (udrn) is read . always set this bit to zero when writing to ucsrna. ? bit 2 ? upen: usart parity error n this bit is set if the next character in the receive buffer had a parity error when received and the parity checking was enabled at that point (upm1n = 1). this bit is valid until the receive buffer (udrn) is read. always set this bit to zero when writing to ucsrna. ? bit 1 ? u2xn: double the usart transmission speed n this bit only has effect for the asynchronous operation. w rite this bit to zero when using syn- chronous operation. w riting this bit to one will reduce the divisor of th e baud rate divider from 16 to 8 effectively dou- bling the transfer rate for asynchronous communication. ? bit 0 ? mpcmn: multi-processor communication mode n this bit enables the multi-processor communication mode. w hen the mpcmn bit is written to one, all the incoming frames received by the usart receiver that do not contain address infor- mation will be ignored. the transmitter is unaffe cted by the mpcmn setting. for more detailed information see ?multi-processor communication mode? on page 188 . 19.11.3 ucsrnb ? usart contro l and status register n b ? bit 7 ? rxcien: rx comp lete interrupt enable n w riting this bit to one enables interrupt on th e rxc flag. a usart rece ive complete interrupt will be generated only if the rxcie bi t is written to one, the global interrupt flag in sreg is writ- ten to one and the rxc bit in ucsrna is set. ? bit 6 ? txcien: tx complete interrupt enable n w riting this bit to one enables interrupt on the txcn flag. a usart transmit complete interrupt will be generated only if the txcien bit is written to one, the global interrupt flag in sreg is written to one and the txcn bit in ucsrna is set. bit 76543210 (0xc1) rxcien txcien udrien rxenn txenn ucszn2 rxb8n txb8n ucsrnb read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w rr/ w initial value00000000 195 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 ? bit 5 ? udrien: usart data register empty interrupt enable w riting this bit to one enables interrupt on the udren flag. a data register empty interrupt will be generated only if the udrien bit is written to one, the global interrupt flag in sreg is written to one and the udren bit in ucsrna is set. ? bit 4 ? rxenn: receiver enable n w riting this bit to one enables the usart receiv er. the receiver will override normal port oper- ation for the rxd pin when enabled. disabling the receiver will flush the receive buffer invalidating the fen, dorn, and upen flags. ? bit 3 ? txenn: transmitter enable n w riting this bit to on e enables the usart transmitter. th e transmitter will override normal port operation for the txd pin when enabled. the disa bling of the transmitter (writing txenn to zero) will not become effective until ongoing a nd pending transmissions are completed, i.e., when the transmit shift register and transmit buffer register do not contain data to be trans- mitted. w hen disabled, the transmitter will no longer override the txd port. ? bit 2 ? ucszn2: character size n the ucszn2 bits combined with the ucsz1n:0 bit in ucsrnc sets the number of data bits (character size) in a frame the receiver and transmitter use. ? bit 1 ? rxb8n: receive data bit 8 n rxb8n is the ninth data bit of the received char acter when operating with serial frames with nine data bits. must be read before reading the low bits from udrn. ? bit 0 ? txb8n: transmit data bit 8 n txb8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. must be written before writing the low bits to udrn. 19.11.4 ucsrnc ? usart contro l and status register n c ? bit 6 ? umseln: usart mode select n this bit selects between asynchronous and synchronous mode of operation. ? bit 5:4 ? upmn[1:0]: parity mode these bits enable and set type of parity generation and check. if enabled, the transmitter will automatically generate and send the parity of th e transmitted data bits within each frame. the bit 76543210 (0xc2) ? umseln upmn1 upmn0 usbsn ucszn1 ucszn0 ucpoln ucsrnc read/ w rite r r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 1 1 0 table 19-8. umseln bit settings umseln mode 0 asynchronous operation 1 synchronous operation 196 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 receiver will generate a parity value for the in coming data and compare it to the upm0n setting. if a mismatch is detected, the upen flag in ucsrna will be set. ? bit 3 ? usbsn: stop bit select this bit selects the number of stop bits to be inserted by the transmitter. the receiver ignores this setting. ? bit 2:1 ? ucszn[1:0]: character size the ucszn[1:0] bits combined with the ucszn2 bit in ucsrnb sets the number of data bits (character size) in a frame the receiver and transmitter use. ? bit 0 ? ucpoln: clock polarity this bit is used for synchronous mode only. w rite this bit to zero when asynchronous mode is used. the ucpoln bit sets the relationship between data output change and data input sample, and the synchronous clock (xck). table 19-9. upm bits settings upmn1 upmn0 parity mode 00disabled 01reserved 1 0 enabled, even parity 1 1 enabled, odd parity table 19-10. usbsn bit settings usbsn stop bit(s) 01-bit 12-bit table 19-11. ucsz bits settings ucszn2 ucszn1 ucszn0 character size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 100reserved 101reserved 110reserved 1 1 1 9-bit table 19-12. ucpoln bit settings ucpoln transmitted data changed (output of txd pin) received data sample d (input on rxd pin) 0 rising xck edge falling xck edge 1 falling xck edge rising xck edge 197 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 19.11.5 ubrrnl and ubrrnh ? usart baud rate registers ? bit 15:12 ? reserved these bits are reserved for future use. for compatibility with future devices, these bit must be written to zero when ubrrnh is written. ? bit 11:0 ? ubrr[11:0]: usart baud rate register this is a 12-bit register which contains the usart baud rate. the ubrrnh contains the four most significant bits, and the ubrrnl contains the eight least significant bits of the usart baud rate. ongoing transmissions by the tran smitter and receiver will be corrupted if the baud rate is changed. w riting ubrrnl will trigger an immediate update of the bau d rate prescaler. bit 151413121110 9 8 (0xc5) ? ? ? ? ubrrn[11:8] ubrrnh (0xc4) ubrrn[7:0] ubrrnl 76543210 read/ w rite rrrrr/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 00000000 198 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 20. usi ? universal serial interface 20.1 features ? two-wire synchronous data tr ansfer (master or slave) ? three-wire synchronous data transfer (master or slave) ? data received interrupt ? wakeup from idle mode ? in two-wire mode: wake-up from all sleep modes, including power-down mode ? two-wire start condition detect or with interr upt capability 20.2 overview the universal serial interface, or usi, provides the basic hardware resources needed for serial communication. combined with a minimum of cont rol software, the usi allows significantly higher transfer rates and uses less code space than solutions based on software only. interrupts are included to minimize the processor load. a simplified block diagram of the usi is shown in figure 21-1 on page 210 . for the actual place- ment of i/o pins, refer to ?pin configurations? on page 2 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit loca- tions are listed in the ?register descriptions? on page 206 . figure 20-1. universal serial interface, block diagram the 8-bit shift register is directly accessible via the data bus and contains the incoming and outgoing data. the register has no buffering so the data must be read as quickly as possible to ensure that no data is lost. the most signific ant bit is connected to one of two output pins depending of the wire mode configuration. a transparent latch is inserted between the serial register output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. the serial input is always sampled from the data input (di) pin independent of the configuration. data bu s u s ipf u s itc u s iclk u s ic s 0 u s ic s 1 u s ioif u s ioie u s idc u s i s if u s iwm0 u s iwm1 u s i s ie bit7 two-wire clock control unit do (output only) di/ s da (input/open drain) u s ck/ s cl (input/open drain) 4-bit counter u s idr u s i s r dq le u s icr clock hold tim0 comp bit0 [1] 3 0 1 2 3 0 1 2 0 1 2 199 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 the 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. both the serial register and the coun ter are clocked simultaneously by the same clock source. this allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. note that when an external clock source is selected the counter counts both clock edges. in this ca se the counter counts the number of edges, and not the number of bits. the clock can be selected from three different sources: the usck pin, timer/counter0 compare match or from software. the two-wire clock control unit can generate an interrupt when a start condition is detected on the two-wire bus. it can also generate wait states by holding the clock pin low after a start con- dition is detected, or after the counter overflows. 20.3 functional descriptions 20.3.1 three-wire mode the usi three-wire mode is compliant to the serial peripheral interface (spi) mode 0 and 1, but does not have the slave select (ss) pin functionality. however, this feature can be implemented in software if necessary. pin names used by this mode are: di, do, and usck. figure 20-2. three-wire mode operat ion, simplified diagram figure 20-2 on page 199 shows two usi units operating in three-wire mode, one as master and one as slave. the two shift registers are interconnected in such way that after eight usck clocks, the data in each register are interchanged. the same clock also increments the usi?s 4- bit counter. the counter overflow (interrupt) fl ag, or usioif, can therefore be used to deter- mine when a transfer is completed. the clock is generated by the master device software by toggling the usck pin via the port register or by writing a one to the usitc bit in usicr. slave master bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 do di usck bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 do di usck portxn 200 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 20-3. three-wire mode, timing diagram the three-wire mode timing is shown in figure 20-3 on page 200 at the top of the figure is a usck cycle reference. one bit is shifted into th e usi shift register (usidr) for each of these cycles. the usck timing is shown for both exte rnal clock modes. in external clock mode 0 (usics0 = 0), di is sampled at positive edges, and do is changed (data register is shifted by one) at negative edges. external clock mode 1 (usics0 = 1) uses the opposite edges versus mode 0, i.e., samples data at negative and changes the output at positive edges. the usi clock modes corresponds to the spi data mode 0 and 1. referring to the timing diagram ( figure 20-3 on page 200 .), a bus transfer involves the following steps: 1. the slave device and master device sets up its data output and, depending on the proto- col used, enables its output driver (mark a and b). the output is set up by writing the data to be transmitted to the serial data register. enabling of the output is done by set- ting the corresponding bit in the port data direction register. note that point a and b does not have any specific order, but both must be at least one half usck cycle before point c where the data is sampled. this must be done to ensure that the data setup requirement is satisfied. the 4-bit counter is reset to zero. 2. the master generates a clock pulse by software toggling the usck line twice (c and d). the bit value on the slave and master?s data input (di) pin is sampled by the usi on the first edge (c), and the data output is changed on the opposite edge (d). the 4-bit counter will count both edges. 3. step 2. is repeated eight times for a complete register (byte) transfer. 4. after eight clock pulses (i.e., 16 clock edge s) the counter will overfl ow and indicate that the transfer is completed. the data bytes transferred must now be processed before a new transfer can be init iated. the overflow interrupt will wa ke up the processor if it is set to idle mode. depending of the protocol used the slave device can now set its output to high impedance. 20.3.2 spi master operation example the following code demonstrates how to use the usi module as a spi master: spitransfer: sts usidr,r16 ldi r16,(1< 204 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 20-5. two-wire mode, typical timing diagram referring to the timing diagram ( figure 20-5 on page 204 ), a bus transfer in volves the following steps: 1. the a start condition is generated by the master by forcing the sda low line while the scl line is high (a). sda can be forced low either by writing a zero to bit 7 of the shift register, or by setting the corresponding bit in the port register to zero. note that the data direction register bit must be set to one for the output to be enabled. the slave device?s start detector logic ( figure 20-6 on page 204 ) detects the start condition and sets the usisif flag. the flag can generate an interrupt if necessary. 2. in addition, the start detector will hold the scl line low after the master has forced an negative edge on this line (b). this allows the slave to wake up from sleep or complete its other tasks before setting up the shift register to receive the address. this is done by clearing the start condition flag and reset the counter. 3. the master set the first bit to be transferred and releases the scl line (c). the slave samples the data and shift it into the serial register at the positive edge of the scl clock. 4. after eight bits are transferred containing slave address and data direction (read or write), the slave counter overflows and the scl line is forced low (d). if the slave is not the one the master has addressed, it releases the scl line and waits for a new start condition. 5. if the slave is addressed it holds the sda line low during the acknowledgment cycle before holding the scl line low again (i.e., the counter register must be set to 14 before releasing scl at (d)). depending of the r/ w bit the master or slave enables its output. if the bit is set, a master read operation is in progress (i.e., the slave drives the sda line) the slave can hold the scl line low after the acknowledge (e). 6. multiple bytes can now be transmitted, all in same direction, until a stop condition is given by the master (f). or a new start condition is given. if the slave is not able to receive more data it does not acknowledge the data byte it has last received. w hen the master does a read operation it must terminate the operation by force the acknowledge bit low after the last byte transmitted. figure 20-6. start condition detector, logic diagram p s address 1 - 7 8 9 r/w ack ack 1 - 8 9 data ack 1 - 8 9 data sda scl a b d e c f sda scl write( usisif) clock hold usisif dq clr dq clr 205 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 20.3.5 start condition detector the start condition detector is shown in figure 20-6 on page 204 . the sda line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the scl line. the start condition detector is only enabled in two-wire mode. the start condition detector is working asynchronously and can therefore wake up the processor from the power-down sleep mode. however, the protocol used might have restrictions on the scl hold time. therefore, when us ing this feature in this case th e oscillator start-up time set by the cksel fuses (see ?clock systems and their distribution? on page 29 ) must also be taken into the consideration. refer to the usisif bit description on page 206 for further details. 20.3.6 clock speed considerations. maximum frequency for scl and sck is f_ck /4. this is also the maximum data transmit and receieve rate in both two- and three-wire mode. in two-wire slave mode the two-wire clock con- trol unit will hold the scl low unt il the slave is ready to receive more data. this may reduce the actual data rate in two-wire mode. 20.4 alternative usi usage w hen the usi unit is not used for serial communica tion, it can be set up to do alternative tasks due to its flexible design. 20.4.1 half-duplex asynchronous data transfer by utilizing the shift register in three-wire m ode, it is possible to implement a more compact and higher performance uart than by software only. 20.4.2 4-bit counter the 4-bit counter can be used as a stand-alone counter with overflow interrupt. note that if the counter is clocked externally, both clock edges will generate an increment. 20.4.3 12-bit timer/counter combining the usi 4-bit counter and timer/counter0 allows them to be used as a 12-bit counter. 20.4.4 edge triggered external interrupt by setting the counter to maximum value (f) it can function as an additional external interrupt. the overflow flag and interrupt enable bit are th en used for the external interrupt. this feature is selected by the usics1 bit. 20.4.5 software interrupt the counter overflow interrupt can be used as a software interrupt triggered by a clock strobe. 206 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 20.5 register descriptions 20.5.1 usidr ? usi data register the usi uses no buffering of the serial register, i.e., when accessing the data register (usidr) the serial register is accessed directly . if a serial clock occurs at the same cycle the register is written, the register will contain the valu e written and no shift is performed. a (left) shift operation is performed depending of the usics1...0 bits setting. the shift operation can be con- trolled by an external clock edge, by a timer/c ounter0 compare match, or directly by software using the usiclk strobe bit. note that even when no wire mode is selected (usi w m1...0 = 0) both the external data input (di/sda) and the external clock input (u sck/scl) can still be used by the shift register. the output pin in use, do or sda depending on the wire mode, is connected via the output latch to the most significant bit (bit 7) of the data register. the output latch is open (transparent) dur- ing the first half of a serial cloc k cycle when an external clock so urce is selected (usics1 = 1), and constantly open when an internal clock so urce is used (usics1 = 0). the output will be changed immediately when a new msb written as long as the latch is open. the latch ensures that data input is sampled and data output is changed on opposite clock edges. note that the corresponding data direction register to the pin must be set to one for enabling data output from the shift register. 20.5.2 usisr ? usi status register the status register contains interrupt flags, line status flags and the counter value. ? bit 7 ? usisif: start condition interrupt flag w hen two-wire mode is selected, the usisif flag is set (to one) when a start condition is detected. w hen output disable mode or three-wire mode is selected and (usicsx = 0b11 & usiclk = 0) or (usics = 0b10 & usiclk = 0), any edge on the sck pin sets the flag. an interrupt will be generated when the flag is set while th e usisie bit in usicr and the global interrupt enable flag are set. the flag will only be cleared by writing a logical one to the usisif bit. clearing this bit will release the start de tection hold of uscl in two-wire mode. a start condition interr upt will wakeup the processor from all sleep modes. ? bit 6 ? usioif: counter overflow interrupt flag this flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). an interrupt will be generate d when the flag is set while the usioie bit in usicr and the global interrupt enable flag ar e set. the flag will only be cleared if a one is written to the usioif bit. clearing this bit will release the counter overfl ow hold of scl in two-wire mode. a counter overflow interrup t will wakeup the processor from idle sleep mode. bit 7 6 5 4 3 2 1 0 (0xba) msb lsb usidr read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 bit 76543 210 (0xb9) usisif usioif usipf usidc usicnt3 usicnt2 usicnt1 usicnt0 usisr read/ w rite r/ w r/ w r/ w rr/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 207 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 ? bit 5 ? usipf: stop condition flag w hen two-wire mode is selected, the usipf flag is set (one) when a stop condition is detected. the flag is cleared by writing a one to this bit. note that this is not an interrupt flag. this signal is useful when implementing two-wire bus master arbitration. ? bit 4 ? usidc: data output collision this bit is logical one when bit 7 in the shift regi ster differs from the physical pin value. the flag is only valid when two-wire mode is used. this signal is useful when implementing two-wire bus master arbitration. ? bits 3...0 ? usicnt3:0: counter value these bits reflect the current 4-bit counter value. the 4-bit counter value can directly be read or written by the cpu. the 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a timer/counter0 compare match, or by software using usiclk or usitc strobe bits. the clock source depends of the setting of the usics1:0 bits. for external clock operation a special feature is added that allows the clock to be generated by writing to the usitc strobe bit. this feature is enabled by write a one to the usiclk bit while setting an external clock source (usics1 = 1). note that even when no wire mode is selected (usi w m1:0 = 0) the external clock input (usck/scl) are can still be used by the counter. 20.5.3 usicr ? usi control register the control register includes interrupt enable control, wire mode setting, clock select setting, and clock strobe. ? bit 7 ? usisie: start condition interrupt enable setting this bit to one enables the start condition detector interrupt. if there is a pending inter- rupt when the usisie and the globa l interrupt enable flag is set to one, this will immediately be executed. refer to the usisif bit description on page 206 for further details. ? bit 6 ? usioie: counter overflow interrupt enable setting this bit to one enables the counter overflow interrupt. if there is a pending interrupt when the usioie and the global interrupt enable flag is set to one, this will immediately be executed. refer to the usioif bit description on page 206 for further details. ? bit 5:4 ? usiwm1:0: wire mode these bits set the type of wire mode to be us ed. basically only the function of the outputs are affected by these bits. data and clock inputs are not affected by the mode selected and will always have the same function. the counter and shift register can therefore be clocked exter- nally, and data input sampled, even when outputs are disabled. the relations between usi w m1:0 and the usi operation is summarized in table 20-1 on page 208 . bit 7 6 5 4 3 2 1 0 (0xb8) usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc usicr read/ w rite r/ w r/ w r/ w r/ w r/ w r/ ww w initial value 0 0 0 0 0 0 0 0 208 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 note: 1. the di and usck pins are renamed to serial data (sda) and serial clock (scl) respectively to avoid confusion between the modes of operation. ? bit 3:2 ? usics1:0: clock source select these bits set the clock source for the shift register and counter. the data output latch ensures that the output is changed at the opposite edge of the sampling of the data input (di/sda) when using external clock source (usck/scl). w hen software strobe or timer/counter0 compare match clock option is selected, the output latch is transparent and therefore the output is changed immediately. clearing the usics1...0 bits enables software strobe option. w hen using this option, writing a one to the usiclk bit clocks both the shift register and the counter. for external clock source (usics1 = 1), the usiclk bit is no longer used as a strobe, but selects between external clocking and software clocking by the usitc strobe bit. table 20-1. relations between usi w m1:0 and the usi operation usiwm1 usiwm0 description 00 outputs, clock hold, and start detector disabled. port pins operates as normal. 01 three-wire mode. uses do, di, and usck pins. the data output (do) pin overrides the corresponding bit in the port register in this mode. however, the corresponding ddr bit still controls the data direction. w hen the port pin is set as input the pins pull-up is controlled by the port bit. the data input (di) and serial clock (usck) pins do not affect the normal port operation. w hen operating as master, clock pulses are software generated by toggling the port register , while the data direction is set to output. the usitc bit in the usicr regi ster can be used for this purpose. 10 two-wire mode. uses sda (di) and scl (usck) pins (1) . the serial data (sda) and the serial clock (scl) pins are bi-directional and uses open-collector output drives. the output drivers are enabled by setting the corresponding bit for sda and scl in the ddr register. w hen the output driver is enabled for the sda pin, the output driver will force the line sda low if the output of the sh ift register or the corresponding bit in the port register is zero. otherwise the sda line will not be driven (i.e., it is released). w hen the scl pin output driver is enabled the scl line will be forced low if the corresponding bit in the port register is zero, or by the start detector. otherwise the scl line will not be driven. the scl line is held low when a start detector detects a start condition and the output is enabled. clearing the start condition flag (usisif) releases the line. the sda and scl pin inputs is not affected by enabling this mode. pull- ups on the sda and scl port pin are disabled in two-wire mode. 11 two-wire mode. uses sda and scl pins. same operation as for the two-wire mode described above, except that the scl line is also held low when a counter overflow occurs, and is held low until the counter overflow flag (usioif) is cleared. 209 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 table 20-2 shows the relationship between the usics1:0 and usiclk setting and clock source used for the shift register and the 4-bit counter. ? bit 1 ? usiclk: clock strobe w riting a one to this bit location strobes the shift register to shift one step and the counter to increment by one, provided that the usics1...0 bits are set to zero and by doing so the software clock strobe option is selected. the output will change immediately when the clock strobe is exe- cuted, i.e., in the same instruction cycle. the va lue shifted into the shift register is sampled the previous instruction cycle. the bit will be read as zero. w hen an external clock source is selected (usics1 = 1), the usiclk function is changed from a clock strobe to a clock select register. setting the usiclk bit in this case will select the usitc strobe bit as clock sour ce for the 4-bit counter (see table 20-2 on page 209 ). ? bit 0 ? usitc: toggle clock port pin w riting a one to this bit location toggles the usck/scl value either from 0 to 1, or from 1 to 0. the toggling is independent of the setting in the data direction register, but if the port value is to be shown on the pin the ddre4 must be set as output (to one). this feature allows easy clock generation when implementi ng master devices. the bit will be read as zero. w hen an external clock source is selected (usics 1 = 1) and the usiclk bit is set to one, writ- ing to the usitc strobe bit will directly clock th e 4-bit counter. this allows an early detection of when the transfer is done when operating as a master device. table 20-2. relations between the usics1:0 and usiclk setting usics1 usics0 usiclk shift register cl ock source 4-bit counter clock source 0 0 0 no clock no clock 001 software clock strobe (usiclk) software clock strobe (usiclk) 01x timer/counter0 compare match timer/counter0 compare match 1 0 0 external, positive edge external, both edges 1 1 0 external, negative edge external, both edges 1 0 1 external, positive edge so ftware clock st robe (usitc) 1 1 1 external, negative edge software clock strobe (usitc) 210 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 21. ac - analog comparator the analog comparator compares the input values on the positive pin ain0 and negative pin ain1. w hen the voltage on the positive pin ain0 is higher than the voltage on the negative pin ain1, the analog comparator output, aco, is set. the comparator?s output can be set to trigger the timer/counter1 input capture function. in addition, the comparator can trigger a separate interrupt, exclusive to the analog comparator. th e user can select interrupt triggering on com- parator output rise, fall or toggle. a block diagram of the comparator and its surrounding logic is shown in figure 21-1 . the power reduction adc bit, pradc, in ?prr ? power reduction register? on page 45 must be disabled by writing a logical zero to be able to use the adc input mux. figure 21-1. analog comparator block diagram (2) notes: 1. see table 21-1 on page 211 . 2. refer to figure 1-1 on page 2 and figure 13-5 on page 74 for analog comparator pin placement. acbg bandgap reference adc multiplexer output acme aden (1) 211 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 21.1 analog comparator multiplexed input it is possible to select any of the adc7:0 pins to replace the negative input to the analog com- parator. the adc multiplexer is used to select this input, and consequently, the adc must be switched off to utilize this feature. if the analog comparator multiplexer enable bit (acme in adcsrb) is set and the adc is switched off (ade n in adcsra is zero), mux2:0 in admux select the input pin to replace the negative input to the analog comparator, as shown in table 21-1 . if acme is cleared or aden is set, ain1 is applied to the negative input to the analog comparator. table 21-1. analog comparator multiplexed input acme aden mux2:0 analog comparator negative input 0 x xxx ain1 1 1 xxx ain1 1 0 000 adc0 1 0 001 adc1 1 0 010 adc2 1 0 011 adc3 1 0 100 adc4 1 0 101 adc5 1 0 110 adc6 1 0 111 adc7 212 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 21.2 register description 21.2.1 adcsrb ? adc control and status register b ? bit 6 ? acme: analog comparator multiplexer enable w hen this bit is written logic one and the adc is switched off (aden in adcsra is zero), the adc multiplexer selects the negative input to the analog comparator. w hen this bit is written logic zero, ain1 is applied to the negative input of the analog comparator. for a detailed description of this bit, see ?analog comparator multiplexed input? on page 211 . 21.2.2 acsr ? analog comparator control and status register ? bit 7 ? acd: analog comparator disable w hen this bit is written logic one , the power to the analog comparator is switched off. this bit can be set at any time to tu rn off the analog com parator. this will reduce power consumption in active and idle mode. w hen changing the acd bit, the analog comparator interrupt must be disabled by clearing the acie bit in acsr. otherwise an interrupt can occur when the bit is changed. ? bit 6 ? acbg: analog comparator bandgap select w hen this bit is set, a fixed bandgap reference volt age replaces the positive input to the analog comparator. w hen this bit is cleared, ain0 is applied to the positive input of the analog compar- ator. see ?internal voltage reference? on page 50. ? bit 5 ? aco: analog comparator output the output of the analog comparator is synchronized and then directly connected to aco. the synchronization introduces a delay of 1 - 2 clock cycles. ? bit 4 ? aci: analog comparator interrupt flag this bit is set by hardware when a comparator output event triggers the interrupt mode defined by acis1 and acis0. the analog comparator interr upt routine is executed if the acie bit is set and the i-bit in sreg is set. aci is cleared by hardware when executing the corresponding inter- rupt handling vector. alternatively, aci is cleared by writing a logic one to the flag. ? bit 3 ? acie: analog comparator interrupt enable w hen the acie bit is written logic one and the i-bit in the status register is set, the analog com- parator interrupt is activated. w hen written logic zero, the interrupt is disabled. ? bit 2 ? acic: analog comparator input capture enable w hen written logic one, this bit enables the input capture function in timer/counter1 to be trig- gered by the analog comparator. the comparator output is in this case directly connected to the bit 7 6543210 (0x7b) ? acme ? ? ? adts2 adts1 adts0 adcsrb read/ w rite r r/ w rrrr/ w r/ w r/ w initial value 0 0000000 bit 76543210 0x30 (0x50) acd acbg aco aci acie acic acis1 acis0 acsr read/ w rite r/ w r/ w rr/ w r/ w r/ w r/ w r/ w initial value 0 0 n/a 0 0 0 0 0 213 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 input capture front-end logic, making the comp arator utilize the noise canceler and edge select features of the timer/counter1 input capture interrupt. w hen written logic zero, no connection between the analog comparator and the input capture function exists. to make the comparator trigger the timer/counter1 input capture interrupt, the icie1 bit in the timer interrupt mask register (timsk1) must be set. ? bits 1, 0 ? acis1, acis0: analog comparator interrupt mode select these bits determine which comparator events that trigger the analog comparator interrupt. the different settings are shown in table 21-2 on page 213 . w hen changing the acis1/acis0 bits, the analog comparator interrupt must be disabled by clearing its interrupt enable bit in the acsr register. otherwise an interrupt can occur when the bits are changed. 21.2.3 didr1 ? digital in put disable register 1 ? bit 1, 0 ? ain1d, ain0d: ai n1, ain0 digita l input disable w hen this bit is written logic one, the digital input buffer on the ain1/0 pin is disabled. the corre- sponding pin register bit will always re ad as zero when this bit is set. w hen an analog signal is applied to the ain1/0 pin and the digital input from this pin is not needed, this bit should be writ- ten logic one to reduce power consumption in the digital input buffer. table 21-2. acis1/acis0 settings acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle. 01reserved 1 0 comparator interrupt on falling output edge. 1 1 comparator interrupt on rising output edge. bit 76543210 (0x7f) ? ? ? ? ? ? ain1d ain0d didr1 read/ w rite rrrrrrr/ w r/ w initial value 0 0 0 0 0 0 0 0 214 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 22. adc - analog to digital converter 22.1 features ? 10-bit resolution ? 0.5 lsb integral non-linearity ? 2 lsb absolute accuracy ? 13s - 260s conversion time (50khz to 1mhz adc clock) ? up to 15ksps at maximum resolution (200khz adc clock) ? eight multiplexed single ended input channels ? optional left adjustment for adc result readout ? 0 - v cc adc input voltage range ? selectable 1.1v adc reference voltage ? free running or single conversion mode ? adc start conversion by auto tr iggering on interrupt sources ? interrupt on adc conversion complete ? sleep mode no ise canceler 22.2 overview the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p features a 10- bit successive approximation adc. the adc is connected to an 8-channel analog multiplexer which allows eight single-ended voltage inputs cons tructed from the pins of port f. the single- ended voltage inputs refer to 0v (gnd). the adc contains a sample and hold circuit whic h ensures that the input voltage to the adc is held at a constant level during conversion . a block diagram of the adc is shown in figure 22-1 . the adc has a separate analog supply voltage pin, avcc. av cc must not differ more than 0.3v from v cc . see the paragraph ?adc noise canceler? on page 220 on how to connect this pin. internal reference voltages of nominally 1.1v or avcc are provided on-chip. the voltage refer- ence may be externally decoupled at the aref pi n by a capacitor for better noise performance. the power reduction adc bit, pradc, in ?prr ? power reduction register? on page 45 must be written to zero to enable the adc module. 215 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 22-1. analog to digital converter block schematic 22.3 operation the adc converts an analog input voltage to a 10-bit digital value through successive approxi- mation. the minimum value represents gnd and the maximum value represents the voltage on the aref pin minus 1 lsb. optionally, avcc or an internal 1.1v reference voltage may be con- nected to the aref pin by writing to the refsn bits in the admux register. the internal voltage reference may thus be decoupled by an external capacitor at the aref pin to improve noise immunity. the analog input channel is selected by writing to the mux bits in admux. any of the adc input pins, as well as gnd and a fixed bandgap voltage reference, can be selected as single ended inputs to the adc. the adc is enabled by sett ing the adc enable bit, aden in adcsra. volt- age reference and input channel se lections will not go into effect until aden is set. the adc does not consume power when aden is cleared, so it is recommended to switch off the adc before entering power saving sleep modes. the adc generates a 10-bit result which is pr esented in the adc data registers, adch and adcl. by default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the adlar bit in admux. adc conversion complete irq 8-bit data bus 15 0 adc multiplexer select (admux) adc ctrl. & status register (adcsra) adc data register (adch/adcl) mux2 adie adate adsc aden adif adif mux1 mux0 adps0 adps1 adps2 mux3 conversion logic 10-bit dac + - sample & hold comparator internal reference mux decoder mux4 avcc adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 refs0 refs1 adlar + - channel selection adc[9:0] adc multiplexer output differential amplifier aref bandgap reference prescaler single ended / differential selection gnd pos. input mux neg. input mux trigger select adts[2:0] interrupt flags start 216 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch, to ensure that the content of the data registers belongs to the same conversion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been read, and a conversion completes before adch is read, neither register is updated and the result from the conversion is lost. w hen adch is read, adc access to the adch and ad cl registers is re-enabled. the adc has its own interrupt which can be triggered when a conversion completes. w hen adc access to the data registers is prohibited between reading of adch and adcl, the interrupt will trigger even if the result is lost. 22.4 starting a conversion a single conversion is started by writing a l ogical one to the adc start conversion bit, adsc. this bit stays high as long as the conversi on is in progress and will be cleared by hardware when the conversion is completed. if a different data channel is selected while a conversion is in progress, the adc will finish the current conv ersion before performing the channel change. alternatively, a conversion can be triggered automatically by various sources. auto triggering is enabled by setting the adc auto trigger enable bi t, adate in adcsra. the trigger source is selected by setting the adc trig ger select bits, adts in adcsrb (see description of the adts bits for a list of the trigger sources). w hen a positive edge occurs on the selected trigger signal, the adc prescaler is reset and a conversion is st arted. this provides a method of starting con- versions at fixed intervals. if the trigger signal still is set when the conversion completes, a new conversion will not be star ted. if another positive edge occurs on the trigger si gnal during con- version, the edge will be ignored. note that an interrupt flag will be set even if the specific interrupt is disabled or the global interrupt enable bit in sreg is cleared. a conversion can thus be triggered without causing an interrupt. however, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. figure 22-2. adc auto trigger logic using the adc interrupt flag as a trigger source makes the adc start a new conversion as soon as the ongoing conversion has finished. the adc then operates in free running mode, con- stantly sampling and updating the adc data register. the first conversion must be started by writing a logical one to the adsc bit in adcs ra. in this mode the adc will perform successive conversions independently of whether the a dc interrupt flag, adif is cleared or not. ad s c adif s ource 1 s ource n adt s [2:0] conver s ion logic pre s caler s ta rt clk adc . . . . edge detector adate 217 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 if auto triggering is enabled, single conversi ons can be started by writing adsc in adcsra to one. adsc can also be used to determine if a conversion is in progress. the adsc bit will be read as one during a conversion, independently of how the conversion was started. 22.5 prescaling and conversion timing figure 22-3. adc prescaler by default, the successive approximation circ uitry requires an input clock frequency between 50khz and 200khz to get maximum resolution. if a lower resolution than 10 bits is needed, the input clock frequency to the adc can be higher than 200khz to get a higher sample rate. the adc module contains a prescaler, which generates an acceptable adc clock frequency from any cpu frequency above 100khz. the prescaling is set by the adps bits in adcsra. the prescaler starts counting from the moment the adc is switched on by setting the aden bit in adcsra. the prescaler keeps running for as lo ng as the aden bit is set, and is continuously reset when aden is low. w hen initiating a single ended conversion by setti ng the adsc bit in adcsra, the conversion starts at the following rising edge of the adc clock cycle. a normal conversion takes 13 adc clock cycles. the first conversion after the adc is switched on (aden in adcsra is set) takes 25 adc clock cycles in order to initialize the analog circuitry. the actual sample-and-hold takes place 1.5 adc clock cycles after the start of a normal conver- sion and 13.5 adc clock cycles afte r the start of an first conversion. w hen a conversion is complete, the result is written to the adc data re gisters, and adif is set. in single conversion mode, adsc is cleared simultaneously. the software may then set adsc again, and a new conversion will be init iated on the first rising adc clock edge. w hen auto triggering is used, the prescaler is reset when the trigger event occurs. this assures a fixed delay from the trigger event to the start of conversion. in this mode, the sample-and-hold takes place two adc clock cycles after the rising edge on the trigger source signal. three addi- tional cpu clock cycles are used for synchronization logic. w hen using differential mode, along with auto triggering from a source other than the adc conversion complete, each conversion will require 25 adc clocks. this is because the adc must be disabled and re-enabled after every conversion. 7-bit adc pre s caler adc clock s ource ck adp s 0 adp s 1 adp s 2 ck/12 8 ck/2 ck/4 ck/ 8 ck/16 ck/ 3 2 ck/64 reset aden s tart 218 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 in free running mode, a new conversion will be started immediately after the conversion com- pletes, while adsc remains high. for a summary of conversion times, see table 22-1 . figure 22-4. adc timing diagram, first conver sion (single conversion mode) figure 22-5. adc timing diagram, single conversion figure 22-6. adc timing diagram, auto triggered conversion s ign and m s b of result l s b of result adc clock ad s c s ample & hold adif adch adcl cycle number aden 1 212 1 3 14 15 16 17 1 8 19 20 21 22 2 3 24 25 1 2 first conversion next conversion 3 mux and ref s update mux and ref s update conversion complete 1 2 3 4 5 6 7 8 9 10 11 12 1 3 s ign and m s b of result l s b of result adc clock ad s c adif adch adcl cycle number 12 one conversion next conversion 3 s ample & hold mux and ref s update conversion complete mux and ref s update 1 2 3 4 5 6 7 8 9 10 11 12 1 3 s ign and m s b of result l s b of result adc clock trigger s ource adif adch adcl cycle number 12 one conversion next conversion conversion complete prescaler reset adate prescaler reset s ample & hold mux and ref s update 219 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 22-7. adc timing diagram, free running conversion 22.6 changing channel or reference selection the muxn and refs1:0 bits in the admux register are single buffered through a temporary register to which the cpu has random access. this ensures that the channels and reference selection only takes place at a safe point dur ing the conversion. the channel and reference selection is continuously updated until a conversion is started. once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the adc. con- tinuous updating resumes in the last adc clock cycle before the conversion completes (adif in adcsra is set). note that the conversion star ts on the following rising adc clock edge after adsc is written. the user is thus advised not to write new channel or reference selection values to admux until one adc clock cycle after adsc is written. if auto triggering is used, the exact time of t he triggering event can be indeterministic. special care must be taken when updating the admux register, in order to control which conversion will be affected by the new settings. if both adate and aden is written to one, an interrupt event can occur at any time. if the admux register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. admux can be safely updated in the following ways: a. w hen adate or aden is cleared. b. during conversion, minimum one adc clock cycle after the trigger event. c. after a conversion, before the interrupt flag used as trigger source is cleared. w hen updating admux in one of these conditions, t he new settings will affect the next adc conversion. table 22-1. adc conversion time condition sample & hold (cycles from start of conversion) conversion time (cycles) first conversion 13.5 25 normal conversions, single ended 1.5 13 auto triggered conversions 2 13.5 11 12 1 3 s ign and m s b of result l s b of result adc clock ad s c adif adch adcl cycle number 12 one conversion next conversion 3 4 conversion complete s ample & hold mux and ref s update 220 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 22.6.1 adc input channels w hen changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: in single conversion mode, always select the channel before starting the conversion. the chan- nel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the conversion to complete before changing the channel selection. in free running mode, always select the channel before starting the first conversion. the chan- nel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the first conversion to complete, and then change the channel selection. since the next conver sion has already started automati cally, the next result will reflect the previous channel selection. subsequent conversions will refl ect the new channel selection. 22.6.2 adc voltage reference the reference voltage for the adc (v ref ) indicates the conversion range for the adc. single ended channels that exceed v ref will result in code s close to 0x3ff. v ref can be selected as either avcc, internal 1.1v reference, or external aref pin. avcc is connected to the adc through a passive switch. the internal 1.1v reference is gener- ated from the internal bandgap reference (v bg ) through an internal buffer. in either case, the external aref pin is directly connected to the adc, and the reference voltage can be made more immune to noise by connecting a capacitor between the aref pin and ground. v ref can also be measured at the aref pin with a high impedant voltmeter. note that v ref is a high impedant source, and only a capacitive load should be connected in a system. if the user has a fixed voltage source connected to the aref pin, the user may not use the other reference voltage options in the ap plication, as they will be shorte d to the external voltage. if no external voltage is applied to the aref pin, the user may switch between avcc and 1.1v as reference selection. the first adc conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. 22.7 adc noise canceler the adc features a noise canceler that enables conversion during sleep mode to reduce noise induced from the cpu core and other i/o peripherals. the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the following procedure should be used: a. make sure that the adc is enabled and is not busy converting. single conversion mode must be selected and the adc conversion complete interrupt must be enabled. b. enter adc noise reduction mode (or idle mode). the adc will start a conversion once the cpu has been halted. c. if no other interrupts occur before the adc conversion completes, the adc interrupt will wake up the cpu and execute the adc co nversion complete in terrupt routine. if another interrupt wakes up the cpu before the adc conversion is complete, that interrupt will be executed, and an adc conv ersion complete inte rrupt request will be generated when the adc conversion complete s. the cpu will remain in active mode until a new sleep command is executed. note that the adc will not be automatically turned off when entering other sleep modes than idle mode and adc noise reduction mode. the user is advised to write zero to aden before enter- ing such sleep modes to avoid excessive power consumption. 221 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 22.7.1 analog input circuitry the analog input circuitry for single ended channels is illustrated in figure 22-8. an analog source applied to adcn is subjected to the pin capacitance and input leakage of that pin, regard- less of whether that channel is selected as input for the adc. w hen the channel is selected, the source must drive the s/h capacitor through the series resistance (combined resistance in the input path). the adc is optimized for analog signals wit h an output impedance of approximately 10 k or less. if such a source is used, the sampling time will be negligible. if a source with higher imped- ance is used, the sampling time will depend on how long time the source nee ds to charge the s/h capacitor, with can vary widely. the user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the s/h capacitor. signal components higher th an the nyquist frequency (f adc /2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. the user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the adc. figure 22-8. analog input circuitry adcn i ih 1..100 k c s /h = 14 pf v cc /2 i il 222 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 22.7.2 analog noise canceling techniques digital circuitry inside and outside the device ge nerates emi which might affect the accuracy of analog measurements. if conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. keep analog signal paths as short as possible. make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. b. the avcc pin on the device should be connected to the digital v cc supply voltage via an lc network as shown in figure 22-9 . c. use the adc noise canceler function to reduce induced noise from the cpu. d. if any adc port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. figure 22-9. adc power connections vcc gnd 100nf ground plane (adc0) pf0 (adc7) pf7 (adc1) pf1 (adc2) pf2 (adc3) pf3 (adc4) pf4 (adc5) pf5 (adc6) pf6 aref gnd avcc 52 53 54 55 56 57 58 59 60 61 61 62 62 63 63 64 64 1 51 dnc pa0 10 ? 223 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 22.7.3 adc accuracy definitions an n-bit single-ended adc converts a voltage linearly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highest code is read as 2 n -1. several parameters describe the deviation from the ideal behavior: ? offset: the deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 lsb). ideal value: 0 lsb. figure 22-10. offset error ? gain error: after adjusting for offset, the gain error is found as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5 lsb below maximum). ideal value: 0 lsb figure 22-11. gain error ? integral non-linearity (inl): after adjusting for offset and gain error, the inl is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0 lsb. output code v ref input voltage ideal adc actual adc offset error output code v ref input voltage ideal adc actual adc gain error 224 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 22-12. integral non-linearity (inl) ? differential non-linearity (dnl): the maximum de viation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 lsb). ideal value: 0 lsb. figure 22-13. differential non-linearity (dnl) ? quantization error: due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 lsb wide) will c ode to the same value. always 0.5 lsb. ? absolute accuracy: the maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. this is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5 lsb. output code v ref input voltage ideal adc actual adc inl output code 0x 3 ff 0x000 0 v ref input voltage dnl 1 l s b 225 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 22.8 adc conversion result after the conversion is complete (adif is high ), the conversion result can be found in the adc result registers (adcl, adch). for single ended conversion, the result is where v in is the voltage on the selected input pin and v ref the selected voltage reference (see table 22-3 on page 227 and table 22-4 on page 228 ). 0x000 represents analog ground, and 0x3ff represents the selected reference voltage minus one lsb. figure 22-14. differential measurement range adc v in 1024 ? v ref -------------------------- = adc v pos v neg ? () 512 ? v ref ---------------------------------------------------- - = 0 output code 0x1ff 0x000 v ref differential input voltage (volts) 0x 3 ff 0x200 - v ref 226 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 admux = 0xfb (adc3 - adc2, 1.1v reference, left adjusted result) voltage on adc3 is 300 mv, voltage on adc2 is 500 mv. adcr = 512 * (300 - 500) / 1100 = -93 = 0x3a3 . adcl will thus read 0xc0 , and adch will read 0xd8. w riting zero to adla r right adjusts the result: adcl = 0xa3, adch = 0x03. table 22-2. correlation between input voltage and output codes v adcn read code corresponding decimal value v adcm + v ref 0x1ff 511 v adcm + 511 / 512 v ref 0x1ff 511 v adcm + 510 / 512 v ref 0x1fe 510 ... ... ... v adcm + 1 / 512 v ref 0x001 1 v adcm 0x000 0 v adcm - 1 / 512 v ref 0x3ff -1 ... ... ... v adcm - 511 / 512 v ref 0x201 -511 v adcm - v ref 0x200 -512 227 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 22.9 register description 22.9.1 admux ? adc multiplexer selection register ? bit 7:6 ? refs1:0: reference selection bits these bits select the voltage reference for the adc, as shown in table 22-3 . if these bits are changed during a conversion, the change will not go in effect until this conversion is complete (adif in adcsra is set). the internal voltage reference options may not be used if an external reference voltage is being applied to the aref pin. ? bit 5 ? adlar: adc left adjust result the adlar bit affects the presentation of the adc conversion result in the adc data register. w rite one to adlar to left adjust the result. otherwise, the result is right adjusted. changing the adlar bit will affect t he adc data register immediately, regardless of any ongoing conver- sions. for a complete description of this bit, see ?adcl and adch ? adc data register? on page 230 . ? bits 4:0 ? mux4:0: analog channel selection bits the value of these bits selects which combination of analog inputs are connected to the adc. see table 22-4 for details. if these bits are changed during a conversion, the change will not go in effect until this conversion is complete (adif in adcsra is set). bit 76543210 (0x7c) refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 admux read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 table 22-3. voltage reference selections for adc refs1 refs0 voltage reference selection 0 0 aref, internal vref turned off 0 1 avcc with external capacitor at aref pin 10reserved 1 1 internal 1.1v voltage reference with external capacitor at aref pin 228 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 table 22-4. input channel selections mux4..0 single ended input positive differen tial input negative differential input 00000 adc0 n/a 00001 adc1 00010 adc2 00011 adc3 00100 adc4 00101 adc5 00110 adc6 00111 adc7 01000 01001 01010 01011 01100 01101 01110 01111 10000 adc0 adc1 10001 adc1 adc1 10010 n/a adc2 adc1 10011 adc3 adc1 10100 adc4 adc1 10101 adc5 adc1 10110 adc6 adc1 10111 adc7 adc1 11000 adc0 adc2 11001 adc1 adc2 11010 adc2 adc2 11011 adc3 adc2 11100 adc4 adc2 11101 adc5 adc2 11110 1.1v (v bg ) n/a 11111 0v (gnd) 229 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 22.9.2 adcsra ? adc control and status register a ? bit 7 ? aden: adc enable w riting this bit to one enables the adc. by writing it to zero, the adc is turned off. turning the adc off while a conversion is in prog ress, will terminate this conversion. ? bit 6 ? adsc: adc start conversion in single conversion mode, write this bit to one to start each conversion. in free running mode, write this bit to one to start the first conversion. the first conversion after adsc has been written after the adc has been enabled, or if adsc is written at the same time as the adc is enabled, will take 25 adc clock cycles instead of the norma l 13. this first conversi on performs initializa- tion of the adc. adsc will read as one as long as a conversion is in progress. w hen the conversion is complete, it returns to zero. w riting zero to this bit has no effect. ? bit 5 ? adate: adc auto trigger enable w hen this bit is written to one, auto triggering of the adc is enabled. the adc will start a con- version on a positive edge of the selected trigger signal. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb. ? bit 4 ? adif: adc interrupt flag this bit is set when an adc conversion completes and the data registers are updated. the adc conversion complete interrupt is executed if the adie bit and the i-bit in sreg are set. adif is cleared by hardware when executing th e corresponding interrupt handling vector. alter- natively, adif is cleared by writing a logical one to the flag. beware that if doing a read-modify- w rite on adcsra, a pending interrupt can be dis abled. this also applies if the sbi and cbi instructions are used. ? bit 3 ? adie: adc interrupt enable w hen this bit is written to one and the i-bit in sreg is set, the adc conversion complete inter- rupt is activated. ? bits 2:0 ? adps[2:0]: adc prescaler select bits these bits determine the division factor between the xtal frequency and the input clock to the adc. bit 76543210 (0x7a) aden adsc adate adif adie adps2 adps1 adps0 adcsra read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value00000000 230 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 22.9.3 adcl and adch ? adc data register 22.9.3.1 adlar = 0 22.9.3.2 adlar = 1 w hen an adc conversion is complete, the result is found in these two registers. w hen adcl is read, the adc data register is not updated until adch is read. consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch. the adlar bit in admux, and the muxn bits in admux affect the way the result is read from the registers. if adlar is set, the result is left adjusted. if adla r is cleared (default), the result is right adjusted. ? adc9:0: adc conversion result these bits represent the result from the conversion, as detailed in ?adc conversion result? on page 225 . table 22-5. adc prescaler selections adps2 adps1 adps0 division factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 111 128 bit 151413121110 9 8 (0x79) ? ? ? ? ? ? adc9 adc8 adch (0x78) adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl 76543210 read/ w rite rrrrrrrr rrrrrrrr initial value 0 0 0 0 0 0 0 0 00000000 bit 151413121110 9 8 adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch adc1 adc0 ? ? ? ? ? ?adcl 76543210 read/ w rite rrrrrrrr rrrrrrrr initial value 0 0 0 0 0 0 0 0 00000000 231 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 22.9.4 adcsrb ? adc control and status register b ? bit 7 ? reserved this bit is reserved for future use. to ensure co mpatibility with future de vices, this bit must be written to zero when adcsrb is written. ? bit 2:0 ? adts2:0: adc auto trigger source if adate in adcsra is written to one, the value of these bits selects which source will trigger an adc conversion. if adate is cleared, the adts2:0 settings will have no effect. a conversion will be triggered by the risi ng edge of the selected interrupt flag . note that switch ing from a trig- ger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. if aden in adcsra is set, this will start a conversion. switching to free running mode (adts[2:0]=0) will not cause a trigger event, even if t he adc interrupt flag is set . 22.9.5 didr0 ? digital in put disable register 0 ? bit 7:0 ? adc7d:adc0d: ad c7:0 digital input disable w hen this bit is written logic one, the digital input buffer on the corresponding adc pin is dis- abled. the corresponding pin re gister bit will always read as zero when this bit is set. w hen an analog signal is applied to the adc7:0 pin and the di gital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. bit 76543210 (0x7b) ? acme ? ? ? adts2 adts1 adts0 adcsrb read/ w rite r r/ w rrrr/ w r/ w r/ w initial value 00000000 table 22-6. adc auto trigger source selections adts2 adts1 adts0 trigger source 0 0 0 free running mode 0 0 1 analog comparator 0 1 0 external interrupt request 0 0 1 1 timer/counter0 compare match 1 0 0 timer/counter0 overflow 1 0 1 timer/counter compare match b 1 1 0 timer/counter1 overflow 1 1 1 timer/counter1 capture event bit 76543210 (0x7e) adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d didr0 read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 232 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 23. jtag interface and on-chip debug system 23.1 features ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan ca pabilities according to the i eee std. 1149.1 (jtag) standard ? debugger access to: ? all internal peripheral units ? internal and external ram ? the internal register file ?program counter ? eeprom and flash memories ? extensive on-chip debug support for break conditions, including ? avr break instruction ? break on change of program memory flow ? single step break ? program memory break points on single address or address range ? data memory break points on si ngle address or address range ? programming of flash, eeprom , fuses, and lock bits th rough the jtag interface ? on-chip debugging supported by avr studio ? 23.2 overview the avr ieee std. 1149.1 compliant jtag interface can be used for ? testing pcbs by using the jtag boundary-scan capability ? programming the non-volatile memories, fuses and lock bits ? on-chip debugging a brief description is given in the following se ctions. detailed descriptions for programming via the jtag interface, and using the boundary-scan chain can be found in the sections ?program- ming via the jtag interface? on page 304 and ?ieee 1149.1 (jtag) bo undary-scan? on page 239 , respectively. the on-chip debug support is considered being private jtag instructions, and distributed within atmel and to selected third party vendors only. figure 23-1 shows a block diagram of the jtag interface and the on-chip debug system. the tap controller is a state machine controlled by the tck and tms signals. the tap controller selects either the jtag instruction register or one of several data registers as the scan chain (shift register) between the tdi ? input and tdo ? output. the instruction register holds jtag instructions controlling the be havior of a data register. the id-register, bypass register, and the bou ndary-scan chain are the data registers used for board-level testing. the jtag programming interface (actually consisting of several physical and virtual data registers) is used for serial programming via the jtag interface. the internal scan chain and break point scan chain are used for on-chip debugging only. 233 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 23.3 tap ? test access port the jtag interface is accessed through four of the avr?s pins. in jtag terminology, these pins constitute the test access port ? tap. these pins are: ? tms: test mode select. this pin is used for navigating through the tap-controller state machine. ? tck: test clock. jtag operation is synchronous to tck. ? tdi: test data in. serial input data to be shifted in to the instruction register or data register (scan chains). ? tdo: test data out. serial output data from instruction register or data register. the ieee std. 1149.1 also specifies an optional tap signal; trst ? test reset ? which is not provided. w hen the jtagen fuse is unprogrammed, these four tap pins are normal port pins and the tap controller is in reset. w hen programmed and th e jtd bit in mcucsr is cleared, the tap pins are internally pulled high and the jtag is enabled for boundary-scan and programming. the device is shipped with this fuse programmed. for the on-chip debug system, in addition to the jtag interface pins, the reset pin is moni- tored by the debugger to be able to detect external reset sources. the debugger can also pull the reset pin low to reset the whole system, assuming only open collectors on the reset line are used in the application. 234 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 23-1. block diagram tap controller tdi tdo tck tm s fla s h memory avr cpu digital peripheral unit s jtag / avr core communication interface breakpoint unit flow control unit ocd s tatu s and control internal s can chain m u x in s truction regi s ter id regi s ter bypa ss regi s ter jtag programming interface pc instruction address data breakpoint s can chain addre ss decoder analog peripherial unit s i/o port 0 i/o port n boundary s can chain analog inputs control & clock lines device boundary 235 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 23-2. tap controller state diagram 23.4 tap controller the tap controller is a 16-state finite state machine that controls the operation of the boundary- scan circuitry, jtag programming circuitry, or on-chip debug system. the state transitions depicted in figure 23-2 depend on the signal present on tm s (shown adjacent to each state transition) at the time of the rising edge at tck. the initial state after a power-on reset is test- logic-reset. as a definition in this document, the lsb is shifted in and out first for all shift registers. assuming run-test/idle is the present state, a typical scenario for using the jtag interface is: ? at the tms input, apply the sequence 1, 1, 0, 0 at the rising edges of tck to enter the shift instruction register ? shift-ir state. w hile in this state, shift the four bits of the jtag instructions into the jtag instruction register from the tdi input at the rising edge of tck. the tms input must be held low during input of the 3 lsbs in order to remain in the shift-ir state. the msb of the instruction is shifted in when this state is left by setting tms high. w hile the instruction is shifted in from the tdi pin, the captured ir-state 0x01 is shifted out on the tdo pin. the jtag instruction selects a partic ular data register as path between tdi and tdo and controls the circuitry surrounding the selected data register. test-logic-reset run-test/idle s hift-dr exit1-dr pause-dr exit2-dr update-dr s elect-ir s can capture-ir s hift-ir exit1-ir pause-ir exit2-ir update-ir s elect-dr s can capture-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 236 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 ? apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. the instruction is latched onto the parallel output from the shift register path in the update-ir state. the exit-ir, pause- ir, and exit2-ir states are only used for navigating the state machine. ? at the tms input, apply the sequence 1, 0, 0 at the rising edges of tck to enter the shift data register ? shift-dr state. w hile in this state, upload the se lected data register (selected by the present jtag instruction in the jtag instruction register) from the tdi input at the rising edge of tck. in order to remain in the shift-dr state, the tms input must be held low during input of all bits except the msb. the msb of the data is shifted in when this state is left by setting tms high. w hile the data register is shifted in from the tdi pin, the parallel inputs to the data register captured in the capture-dr state is shifted out on the tdo pin. ? apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. if the selected data register has a latched parallel-output, the latching takes place in the update-dr state. the exit-dr, pause-dr, and exit2-dr states are only used for navigating the state machine. as shown in the state diagram, the run-test/idle state need not be entered between selecting jtag instruction and using data registers, and some jtag instructions may select certain functions to be performed in the run-test/idle, making it unsuitable as an idle state. note: independent of the initial state of the tap c ontroller, the test-logic-r eset state can always be entered by holding tms high for five tck clock periods. for detailed information on the jtag specification, refer to the literature listed in ?bibliography? on page 238 . 23.5 using the b oundary-scan chain a complete description of the boundary-sc an capabilities are gi ven in the section ?ieee 1149.1 (jtag) boundary-scan? on page 239 . 23.6 using the on-c hip debug system as shown in figure 23-1 on page 234 , the hardware support for on-chip debugging consists mainly of ? a scan chain on the interface between the internal avr cpu and the internal peripheral units. ? break point unit. ? communication interface between the cpu and jtag system. all read or modify/write operations needed for implementing the debugger are done by applying avr instructions via the internal avr cpu scan chain. the cpu sends the result to an i/o memory mapped location which is part of the communication interface between the cpu and the jtag system. the break point unit implements break on change of program flow, single step break, two program memory break points, and two combined break points. together, the four break points can be configured as either: ? 4 single program memory break points. ? 3 single program memory break point + 1 single data memory break point. ? 2 single program memory break points + 2 single data memory break points. ? 2 single program memory break points + 1 program memory break point with mask (?range break point?). ? 2 single program memory break points + 1 da ta memory break point with mask (?range break point?). 237 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 a debugger, like the avr studio, may however use one or more of these resources for its inter- nal purpose, leaving less flexibility to the end-user. a list of the on-chip debug specific jtag instructions is given in ?on-chip debug specific jtag instructions? on page 237 . the jtagen fuse must be programmed to enable the jtag test access port. in addition, the ocden fuse must be programmed and no lock bits must be set for the on-chip debug system to work. as a security feature, the on-chip debug system is disabled when either of the lb1 or lb2 lock bits are set. otherwise, the on-chi p debug system would have provided a back-door into a secu red device. the avr studio enables the user to fully contro l execution of programs on an avr device with on-chip debug capability, avr in- circuit emulator, or the built-i n avr instruction set simulator. avr studio ? supports source level execution of assembly programs assembled with atmel cor- poration?s avr assembler and c programs compiled with third party vendors? compilers. avr studio runs under microsoft ? w indows ? 95/98/2000, w indows nt ? and w indows xp ? . for a full description of the avr studio, please re fer to the avr studio user guide. only high- lights are presented in this document. all necessary execution commands are available in avr studio, both on source level and on disassembly level. the user can execute the program, single step through the code either by tracing into or stepping over functions, step out of functions, place the cursor on a statement and execute until the statement is reached, stop th e execution, and reset the execution target. in addition, the user can have an unlimited number of code break points (using the break instruction) and up to two data memory break points, alternatively combined as a mask (range) break point. 23.7 on-chip debug specific jtag instructions the on-chip debug support is considered being private jtag instructions, and distributed within atmel and to selected third party vendors only. instruction opcodes are listed for reference. 23.7.1 private0; 0x8 private jtag instruction for accessing on-chip debug system. 23.7.2 private1; 0x9 private jtag instruction for accessing on-chip debug system. 23.7.3 private2; 0xa private jtag instruction for accessing on-chip debug system. 23.7.4 private3; 0xb private jtag instruction for accessing on-chip debug system. 23.8 using the jtag pr ogramming capabilities programming of avr parts via jtag is performed via the 4-pin jtag port, tck, tms, tdi, and tdo. these are the only pins that need to be controlled/observed to perform jtag program- ming (in addition to power pins). it is not requi red to apply 12v externally. the jtagen fuse must be programmed and the jtd bit in the mcucr register must be cleared to enable the jtag test access port. see ?boundary-scan related register in i/o memory? on page 265 . 238 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 the jtag programmi ng capability supports: ? flash programming and verifying. ? eeprom programming and verifying. ? fuse programming and verifying. ? lock bit programming and verifying. the lock bit security is exactly as in parallel programming mode. if the lock bits lb1 or lb2 are programmed, the ocden fuse cannot be programmed unless first doing a chip erase. this is a security feature that ensures no back-door exists for reading out the content of a secured device. the details on programming through the jtag interface and programming specific jtag instructions are given in the section ?programming via the jtag interface? on page 304 . 23.9 on-chip debug related register in i/o memory 23.9.1 ocdr ? on-chi p debug register the ocdr register provides a co mmunication channel from the running pr ogram in the micro- controller to the debugger. the cpu can transfer a byte to the debugger by writing to this location. at the same time, an in ternal flag; i/o debug register dirty ? idrd ? is set to indicate to the debugger that the register has been written. w hen the cpu reads the ocdr register the 7 lsb will be from the ocdr regi ster, while the msb is the idrd bit. the debugger clears the idrd bit when it has read the information. in some avr devices, this register is shared with a standard i/o location. in this case, the ocdr register can only be accessed if the ocden fuse is programmed, and the debugger enables access to the ocdr register. in all other cases, the standard i/o location is accessed. refer to the debugger documentation for further information on how to use this register. 23.10 bibliography for more information about general boundary-scan, the following literature can be consulted: ? ieee: ieee std. 1149.1-1 990. ieee standard test acce ss port and boundary-scan architecture, ieee, 1993. ? colin maunder: the board designers guide to testable logic circuits, addison- w esley, 1992. bit 7 6543210 0x31 (0x51) msb/idrd lsb ocdr read/ w rite r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w initial value 0 0000000 239 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 24. ieee 1149.1 (jtag) boundary-scan 24.1 features ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities acco rding to the jtag standard ? full scan of all port functions as well as analog circuitry having off-chip connections ? supports the optional idcode instruction ? additional public avr_reset instruction to reset the avr 24.2 system overview the boundary-scan chain has the capability of drivin g and observing the logi c levels on the digi- tal i/o pins, as well as the boundary between digi tal and analog logic for analog circuitry having off-chip connections. at system level, all ics having jtag capabilities ar e connected serially by the tdi/tdo signals to form a long shift register. an external controller sets up the devices to drive values at their output pins, and observe the input values received from other devices. the controller compares the received data with the expected result. in this way, boundary-scan pro- vides a mechanism for testing interconnections and integrity of components on printed circuits boards by using the four tap signals only. the four ieee 1149.1 defined mandatory jtag in structions idcode, bypass, sample/pre- load, and extest, as well as the avr specif ic public jtag instruction avr_reset can be used for testing the print ed circuit board. initial scanning of the data register path will show the id-code of the device, since idcode is the default jtag instruction. it may be desirable to have the avr device in reset during test mode. if not reset, inputs to the device may be deter- mined by the scan operations, and the internal software may be in an undetermined state when exiting the test mode. en tering reset, the outputs of any po rt pin will instantly enter the high impedance state, making the highz instruction redundant. if needed, the bypass instruction can be issued to make the shortest possible scan chain through the device. the device can be set in the reset state either by pulling the external reset pin low, or issuing the avr_reset instruction with appropriate setting of the reset data register. the extest instruction is used for sampling external pins and loading output pins with data. the data from the output latch will be driven out on the pins as soon as the extest instruction is loaded into the jtag ir-register. therefore, the sample/preload should also be used for setting initial values to the scan ring, to avoid damaging the board when issuing the extest instruction for the first time. sample/preload c an also be used for taking a snapshot of the external pins during normal operation of the part. the jtagen fuse must be pr ogrammed and the jtd bit in the i/o register mcucr must be cleared to enable the jtag test access port. w hen using the jtag interface for boundary-scan, using a jtag tck clock frequency higher than the internal chip frequency is possible. the chip clock is not required to run. 240 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 24.3 data registers the data registers relevant for boundary-scan operations are: ? bypass register ? device identification register ? reset register ? boundary-scan chain 24.3.1 bypass register the bypass register consists of a single shift register stage. w hen the bypass register is selected as path between tdi and tdo, the register is reset to 0 when leaving the capture-dr controller state. the bypass register can be used to shorten the scan chain on a system when the other devices are to be tested. 24.3.2 device identification register figure 24-1 shows the structure of the de vice identification register. figure 24-1. the format of the device identification register 24.3.2.1 version version is a 4-bit number identifying the revision of the component. the jtag version number follows the revision of the device. revision a is 0x0, revision b is 0x1 and so on. 24.3.2.2 part number the part number is a 16-bit code identifying the component. the jtag part number for atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p is listed in table 26-6 on page 286 . 24.3.2.3 manufacturer id the manufacturer id is a 11-bit code identifying the manufacturer. the jtag manufacturer id for atmel is 0x1f. see table 26-6 on page 286 . 24.3.3 reset register the reset register is a test data register used to reset the part. since the avr tri-states port pins when reset, the reset register can also replace the function of the unimplemented optional jtag instruction highz. a high value in the reset register corresponds to pulling the external reset low. the part is reset as long as there is a high value present in the reset register. depending on the fuse set- tings for the clock options, the part will remain reset for a reset time-out period (refer to ?clock sources? on page 30 ) after releasing the reset register. the output from this data register is not latched, so the reset will take place immediately, as shown in figure 24-2 on page 241 . msb lsb bit 31 28 27 12 11 1 0 device id version part number manufacturer id 1 4 bits 16 bits 11 bits 1-bit 241 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 24-2. reset register 24.3.4 boundary-scan chain the boundary-scan chain has the capability of driv ing and observing the lo gic levels on the dig- ital i/o pins, as well as the boundary between di gital and analog logic for analog circuitry having off-chip connections. see ?boundary-scan chain? on page 242 for a complete description. 24.4 boundary-scan specifi c jtag instructions the instruction register is 4-bit wide, suppor ting up to 16 instructions. listed below are the jtag instructions useful for boundary-scan operation. note that the optional highz instruction is not implemented, but all outputs with tri-stat e capability can be set in high-impedant state by using the avr_reset instruction, since the initial state for all port pins is tri-state. as a definition in this datasheet, the lsb is shifted in and out first for all shift registers. the opcode for each instruction is shown behind the instruction name in hex format. the text describes which data register is selected as path between tdi and tdo for each instruction. 24.4.1 extest; 0x0 mandatory jtag instruction for selecting the boundary-scan chain as data register for testing circuitry external to the avr package. for port- pins, pull-up disable, output control, output data, and input data are all accessible in the scan chain. for analog ci rcuits having off-chip connections, the interface between the analog and th e digital logic is in the scan chain. the con- tents of the latched outputs of the boundary-scan chain is driven out as soon as the jtag ir- register is loaded with the extest instruction. the active states are: ? capture-dr: data on the external pins are sampled into the boundary-scan chain. ? shift-dr: the internal scan chain is shifted by the tck input. ? update-dr: data from the scan chain is applied to output pins. 24.4.2 idcode; 0x1 optional jtag instruction selecting the 32 bit id-register as data register. the id-register consists of a version number, a device number and the manufacturer code chosen by jedec. this is the default inst ruction after power-up. dq from tdi clockdr avr_re s et to tdo from other internal and external reset s ources internal reset 242 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 the active states are: ? capture-dr: data in the idcode register is sampled into the boundary-scan chain. ? shift-dr: the idcode scan chain is shifted by the tck input. 24.4.3 sample_preload; 0x2 mandatory jtag instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. however, the output latches are not connected to the pins. the boundary-scan chain is selected as data register. the active states are: ? capture-dr: data on the external pins are sampled into the boundary-scan chain. ? shift-dr: the boundary-scan chain is shifted by the tck input. ? update-dr: data from the boundary-scan chain is applied to the output latches. however, the output latches are not connected to the pins. 24.4.4 avr_reset; 0xc the avr specific public jtag instruction for forcing the avr device into the reset mode or releasing the jtag reset source. the tap controller is not reset by this in struction. the one bit reset register is selected as da ta register. note that the reset will be active as long as there is a logic ?one? in the reset chain. the output from this chain is not latched. the active states are: ? shift-dr: the reset register is shifted by the tck input. 24.4.5 bypass; 0xf mandatory jtag instructio n selecting the bypass register for data register. the active states are: ? capture-dr: loads a logic ?0? into the bypass register. ? shift-dr: the bypass register cell between tdi and tdo is shifted. 24.5 boundary-scan chain the boundary-scan chain has the capability of drivin g and observing the logi c levels on the digi- tal i/o pins, as well as the boundary between digi tal and analog logic for analog circuitry having off-chip connection. 24.5.1 scanning the digital port pins figure 24-3 on page 243 shows the boundary-scan cell for a bi-directional port pin with pull-up function. the cell consists of a standard boundar y-scan cell for the pull-up enable ? puexn ? function, and a bi-directional pin cell that comb ines the three signals output control ? ocxn, output data ? odxn, and input data ? idxn, into only a two-stage shift register. the port and pin indexes are not used in the following description the boundary-scan logic is not included in the figures in the datasheet. figure 24-4 on page 244 shows a simple digital port pin as described in the section ?i/o-ports? on page 68 . the bound- ary-scan details from figure 24-3 on page 243 replaces the dashed box in figure 24-4 on page 244 . 243 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 w hen no alternate port function is present, the input data ? id ? corresponds to the pinxn reg- ister value (but id has no synchronizer), output data corresponds to the port register, output control corresponds to the data direction ? dd register, and the pull-up enable ? puexn ? cor- responds to logic expression pud ddxn portxn. digital alternate port functions are connected outside the dotted box in figure 24-4 on page 244 to make the scan chain read the actual pin value. for analog function, there is a direct connec- tion from the external pin to the analog circuit, and a scan chain is inserted on the interface between the digital logic and the analog circuitry. figure 24-3. boundary-scan cell for bi-directional port pin with pull-up function. dq dq g 0 1 0 1 dq dq g 0 1 0 1 0 1 0 1 dq dq g 0 1 port pin (pxn) vcc exte s t to next cell s hiftdr output control (oc) pullup enable (pue) output data (od) input data (id) from last cell updatedr clockdr ff2 ld2 ff1 ld1 ld0 ff0 244 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 24-4. general port pin schematic diagram clk rpx rdx wdx pud s ynchronizer wdx: write ddrx wrx: write portx rrx: read portx regi s ter wpx: write pinx regi s ter pud: pullup di s able clk : i/o clock rdx: read ddrx d l q q re s et q q d q q d clr ddxn pinxn data b u s s leep s leep: s leep control pxn i/o i/o s ee boundary-scan description for details! puexn ocxn odxn idxn puexn: pullup enable for pin pxn ocxn: output control for pin pxn odxn: output data to pin pxn idxn: input data from pin pxn rpx: read portx pin rrx re s et q q d clr portxn wpx 0 1 wrx 245 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 24.5.2 scanning the reset pin the reset pin accepts 5v active low logic fo r standard reset operation, and 12v active high logic for high voltage parallel programming. an observe-only cell as shown in figure 24-5 on page 245 is inserted both for the 5v reset signal; rstt, and the 12v reset signal; rsthv. figure 24-5. observe-only cell 24.5.3 scanning the clock pins the avr devices have many clock options selectable by fuses. these are: internal rc oscilla- tor, external clock, (high frequency) crystal oscillator, low-frequenc y crystal oscillator, and ceramic resonator. figure 24-6 on page 245 shows how each oscillator with extern al connection is supported in the scan chain. the enable signal is supported with a g eneral boundary-scan ce ll, while the oscilla- tor/clock output is attached to an observe-only cell. in addition to the main clock, the timer oscillator is scanned in the same way. the output from the internal rc oscill ator is not scanned, as this oscillator does not have external connections. figure 24-6. boundary-scan cells for os cillators and clock options 0 1 dq from previous cell clockdr s hiftdr to next cell from s ystem pin to s ystem logic ff1 0 1 dq from previous cell clockdr s hiftdr to next cell to s ystem logic ff1 0 1 dq dq g 0 1 from previous cell clockdr updatedr s hiftdr to next cell exte s t from digital logic xtal1/to s c1 xtal2/to s c2 oscillator enable output 246 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 table 24-1 on page 246 summaries the scan registers for th e external clock pin xtal1, oscilla- tors with xtal1/xtal2 connections as well as 32khz timer oscillator. notes: 1. do not enable more than one clock source as main clock at a time. 2. scanning an oscillator output gives unpredictable results as there is a frequency drift between the internal oscillator and the jtag tck clock. if possible, scanning an external clock is preferred. 3. the clock configuration is programmed by fuses. as a fuse is not changed run-time, the clock configuration is considered fixed for a given app lication. the user is advised to scan the same clock option as to be used in the final system. the enable signals are supported in the scan chain because the system logic c an disable clock options in sl eep modes, thereby disconnect- ing the oscillator pins from the scan path if not provided. 24.5.4 scanning the analog comparator the relevant comparator signals regarding boundary-scan are shown in figure 24-7 on page 246 . the boundary-scan cell from figure 24-8 on page 247 is attached to each of these signals. the signals are described in table 24-2 on page 247 . the comparator need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. figure 24-7. analog comparator table 24-1. scan signals for the oscillator (1)(2)(3) enable signal scanned clock line clock option scanned clock line when not used extclken extclk (xtal1) external clock 0 oscon oscck external crystal external ceramic resonator 1 osc32en osc32ck low freq. external crystal 1 acbg bandgap reference adc multiplexer output acme ac_idle aco adcen acd 247 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 24-8. general boundary-scan cell used for signals for comparator and adc table 24-2. boundary-scan signals for the analog comparator signal name direction as seen from the comparator description recommended input when not in use output values when recommended inputs are used ac_idle input turns off analog comparator when true 1 depends upon c code being executed aco output analog comparator output w ill become input to c code being executed 0 acme input uses output signal from adc mux when true 0 depends upon c code being executed acbg input bandgap reference enable 0 depends upon c code being executed 0 1 dq dq g 0 1 from previous cell clockdr updatedr s hiftdr to next cell exte s t to analog circuitry/ to digital logic from digital logic/ from analog ciruitry 248 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 24.5.5 scanning the adc figure 24-9 on page 248 shows a block diagram of the adc with all relevant control and observe signals. the boundary-scan cell from figure 24-5 on page 245 is attached to each of these signals. the adc need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. figure 24-9. analog to digital converter the signals are described briefly in table 24-3 on page 248 . 10-bit dac + - aref prech dacout comp muxen_7 adc_7 muxen_6 adc_6 muxen_5 adc_5 muxen_4 adc_4 muxen_ 3 adc_ 3 muxen_2 adc_2 muxen_1 adc_1 muxen_0 adc_0 neg s el_2 adc_2 neg s el_1 adc_1 neg s el_0 adc_0 extch + - 1x s t aclk ampen 1.11v ref irefen aref vccren dac_9..0 adcen hold prech gnden pa ss en comp s cte s t adcbgen to comparator 1.22v ref acten aref table 24-3. boundary-scan signals for the adc (1) signal name direction as seen from the adc description recommended input when not in use output values when recommended inputs are used, and cpu is not using the adc comp output comparator output 0 0 aclk input clock signal to differential amplifier implemented as s witch-cap filters 00 acten input enable path from differential amplifier to the comparator 00 adcbgen input enable band-gap reference as negative input to comparator 00 adcen input power-on signal to the adc 0 0 ampen input power-on signal to the differential amplifier 00 249 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 dac_9 input bit 9 of digital value to dac 1 1 dac_8 input bit 8 of digital value to dac 0 0 dac_7 input bit 7 of digital value to dac 0 0 dac_6 input bit 6 of digital value to dac 0 0 dac_5 input bit 5 of digital value to dac 0 0 dac_4 input bit 4 of digital value to dac 0 0 dac_3 input bit 3 of digital value to dac 0 0 dac_2 input bit 2 of digital value to dac 0 0 dac_1 input bit 1 of digital value to dac 0 0 dac_0 input bit 0 of digital value to dac 0 0 extch input connect adc channels 0 - 3 to by- pass path around differential amplifier 11 gnden input ground the negative input to comparator when true 00 hold input sample & hold signal. sample analog signal when low. hold signal when high. if differential amplifier is used, this signal must go active when aclk is high. 11 irefen input enables band-gap reference as aref signal to dac 00 muxen_7 input input mux bit 7 0 0 muxen_6 input input mux bit 6 0 0 muxen_5 input input mux bit 5 0 0 muxen_4 input input mux bit 4 0 0 muxen_3 input input mux bit 3 0 0 muxen_2 input input mux bit 2 0 0 muxen_1 input input mux bit 1 0 0 muxen_0 input input mux bit 0 1 1 negsel_2 input input mux for negative input for differential signal, bit 2 00 negsel_1 input input mux for negative input for differential signal, bit 1 00 negsel_0 input input mux for negative input for differential signal, bit 0 00 passen input enable pass-gate of differential amplifier. 11 table 24-3. boundary-scan signals for the adc (1) (continued) signal name direction as seen from the adc description recommended input when not in use output values when recommended inputs are used, and cpu is not using the adc 250 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 note: 1. incorrect setting of the switches in figure 24-9 on page 248 will make signal contention and may damage the part. there are several input choices to the s&h circuitry on the negative input of the output comparator in figure 24-9 on page 248 . make sure only one path is selected from either one adc pin, bandgap reference source, or ground. if the adc is not to be used during scan, the recommended input values from table 24-3 on page 248 should be used. the user is recommended not to use the different ial amplifier during scan. switch-cap based differential amplifier r equires fast operation and accurate timing which is difficult to obtain when used in a scan chain. details concerning operations of the differential amplifier is therefore not provided. the avr adc is based on the analog circuitry shown in figure 24-9 on page 248 with a succes- sive approximation algorithm implemented in the digital logic. w hen used in boundary-scan, the problem is usually to ensure that an applied analog voltage is measured within some limits. this can easily be done without running a successive approximation algorithm: apply the lower limit on the digital dac[9:0] lines, make sure the output from the comparator is low, then apply the upper limit on the digital dac[9:0] lines, and verify the output from the comparator to be high. the adc need not be used for pure connectivity te sting, since all analog inputs are shared with a digital port pin as well. w hen using the adc, remember the following ? the port pin for the adc channel in use must be configured to be an input with pull-up disabled to avoid signal contention. ? in normal mode, a dummy conversion (consisting of 10 comparisons) is performed when enabling the adc. the user is advised to wait at least 200ns after enabling the adc before controlling/observing any adc signa l, or perform a dummy conver sion before using the first result. ? the dac values must be stable at the midpoint value 0x200 when having the hold signal low (sample mode). as an example, consider the task of verifying a 1.5v 5% input signal at adc channel 3 when the power supply is 5.0v and aref is externally connected to v cc . prech input precharge output latch of comparator. (active low) 11 sctest input switch-cap test enable. output from differential amp lifier is sent out to port pin having adc_4 00 st input output of differential amplifier will settle faster if this signal is high first two aclk periods after ampen goes high. 00 vccren input selects vcc as the acc reference voltage. 00 table 24-3. boundary-scan signals for the adc (1) (continued) signal name direction as seen from the adc description recommended input when not in use output values when recommended inputs are used, and cpu is not using the adc the lower limit is: 1024 1.5 v 0,95 5 v ? ?? 291 0x123 == the upper limit is: 1024 1.5 v 1.05 5 v ? ?? 323 0x143 == 251 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 the recommended values from table 24-3 on page 248 are used unless other values are given in the algorithm in table 24-4 on page 251 . only the dac and port pin values of the scan chain are shown. the column ?actions? describes what jtag instruction to be used before filling the boundary-scan register with the succeeding co lumns. the verification should be done on the data scanned out when scanning in the data on the same row in the table. using this algorithm, the timing constraint on the hold signal constrains the tck clock fre- quency. as the algorithm keeps hold high for fi ve steps, the tck clock frequency has to be at least five times the number of scan bits divided by the maximum hold time, t hold,max 24.6 boundary-scan order table 24-5 shows the scan order between tdi and tdo when the boundary-scan chain is selected as data path. bit 0 is the lsb; the first bit scanned in, and the first bit scanned out. the scan order follows the pin-out order as far as possible. therefore, the bits of port a is scanned in the opposite bit order of the other ports. exceptions from the rules are the scan chains for the analog circuits, which constitute the most significant bits of the scan chain regardless of which physical pin they are connected to. in figure 24-3 , pxn data corresponds to ff0, pxn control table 24-4. algorithm for using the adc step actions adcen dac muxen hold prech pa 3 . data pa3. control pa 3 . pull-up_ enable 1 sample_p reload 1 0x200 0x08 1 1 0 0 0 2 extest 1 0x200 0x08 0 1 0 0 0 3 1 0x200 0x08 1 1 0 0 0 4 1 0x123 0x08 1 1 0 0 0 5 1 0x123 0x08 1 0 0 0 0 6 verify the comp bit scanned out to be 0 1 0x200 0x08 1 1 0 0 0 7 1 0x200 0x08 0 1 0 0 0 8 1 0x200 0x08 1 1 0 0 0 9 1 0x143 0x08 1 1 0 0 0 10 1 0x143 0x08 1 0 0 0 0 11 verify the comp bit scanned out to be 1 1 0x200 0x08 1 1 0 0 0 252 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 corresponds to ff1, and pxn. pull-up_enable corresponds to ff2. bit 4, 5, 6, and 7of port f is not in the scan chain, since these pins consti tute the tap pins when the jtag is enabled. table 24-5. atmega169a/169pa/329a/329pa/649a/649p boundary-scan order, 64-pin bit number signal name module 197 ac_idle comparator 196 aco 195 acme 194 ainbg 193 comp adc 192 aclk 191 acten 190 private_signal1 (1) 189 adcbgen 188 adcen 187 ampen 186 dac_9 185 dac_8 184 dac_7 183 dac_6 182 dac_5 181 dac_4 180 dac_3 179 dac_2 178 dac_1 177 dac_0 176 extch 175 gnden 174 hold 173 irefen 172 muxen_7 171 muxen_6 170 muxen_5 169 muxen_4 253 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 168 muxen_3 adc 167 muxen_2 166 muxen_1 165 muxen_0 164 negsel_2 163 negsel_1 162 negsel_0 161 passen 160 prech 159 st 158 vccren 157 pe0.data port e 156 pe0.control 155 pe0.pull-up_enable 154 pe1.data 153 pe1.control 152 pe1.pull-up_enable 151 pe2.data 150 pe2.control 149 pe2.pull-up_enable 148 pe3.data 147 pe3.control 146 pe3.pull-up_enable 145 pe4.data 144 pe4.control 143 pe4.pull-up_enable 142 pe5.data 141 pe5.control 140 pe5.pull-up_enable 139 pe6.data 138 pe6.control 137 pe6.pull-up_enable 136 pe7.data 135 pe7.control 134 pe7.pull-up_enable table 24-5. atmega169a/169pa/329a/329pa/649a/649p boundary-scan order, 64-pin bit number signal name module 254 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 133 pb0.data port b 132 pb0.control 131 pb0.pull-up_enable 130 pb1.data 129 pb1.control 128 pb1.pull-up_enable 127 pb2.data 126 pb2.control 125 pb2.pull-up_enable 124 pb3.data 123 pb3.control 122 pb3.pull-up_enable 121 pb4.data 120 pb4.control 119 pb4.pull-up_enable 118 pb5.data 117 pb5.control 116 pb5.pull-up_enable 115 pb6.data 114 pb6.control 113 pb6.pull-up_enable 112 pb7.data 111 pb7.control 110 pb7.pull-up_enable 109 pg3.data port g 108 pg3.control 107 pg3.pull-up_enable 106 pg4.data 105 pg4.control 104 pg4.pull-up_enable 103 pg5 (observe only) 102 rstt reset logic (observe-only) 101 rsthv table 24-5. atmega169a/169pa/329a/329pa/649a/649p boundary-scan order, 64-pin bit number signal name module 255 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 100 extclken enable signals for main clock/oscillators 99 oscon 98 rcoscen 97 osc32en 96 extclk (xtal1) clock input and oscillators for the main clock (observe-only) 95 oscck 94 rcck 93 osc32ck 92 pd0.data port d 91 pd0.control 90 pd0.pull-up_enable 89 pd1.data 88 pd1.control 87 pd1.pull-up_enable 86 pd2.data 85 pd2.control 84 pd2.pull-up_enable 83 pd3.data 82 pd3.control 81 pd3.pull-up_enable 80 pd4.data 79 pd4.control 78 pd4.pull-up_enable 77 pd5.data 76 pd5.control 75 pd5.pull-up_enable 74 pd6.data 73 pd6.control 72 pd6.pull-up_enable 71 pd7.data 70 pd7.control 69 pd7.pull-up_enable table 24-5. atmega169a/169pa/329a/329pa/649a/649p boundary-scan order, 64-pin bit number signal name module 256 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 68 pg0.data port g 67 pg0.control 66 pg0.pull-up_enable 65 pg1.data 64 pg1.control 63 pg1.pull-up_enable 62 pc0.data port c 61 pc0.control 60 pc0.pull-up_enable 59 pc1.data 58 pc1.control 57 pc1.pull-up_enable 56 pc2.data 55 pc2.control 54 pc2.pull-up_enable 53 pc3.data 52 pc3.control 51 pc3.pull-up_enable 50 pc4.data 49 pc4.control 48 pc4.pull-up_enable 47 pc5.data 46 pc5.control 45 pc5.pull-up_enable 44 pc6.data 43 pc6.control 42 pc6.pull-up_enable 41 pc7.data 40 pc7.control 39 pc7.pull-up_enable 38 pg2.data port g 37 pg2.control 36 pg2.pull-up_enable table 24-5. atmega169a/169pa/329a/329pa/649a/649p boundary-scan order, 64-pin bit number signal name module 257 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 35 pa7.data port a 34 pa7.control 33 pa7.pull-up_enable 32 pa6.data 31 pa6.control 30 pa6.pull-up_enable 29 pa5.data 28 pa5.control 27 pa5.pull-up_enable 26 pa4.data 25 pa4.control 24 pa4.pull-up_enable 23 pa3.data 22 pa3.control 21 pa3.pull-up_enable 20 pa2.data 19 pa2.control 18 pa2.pull-up_enable 17 pa1.data 16 pa1.control 15 pa1.pull-up_enable 14 pa0.data 13 pa0.control 12 pa0.pull-up_enable 11 pf3.data port f 10 pf3.control 9 pf3.pull-up_enable 8pf2.data 7pf2.control 6 pf2.pull-up_enable 5pf1.data 4pf1.control 3 pf1.pull-up_enable 2pf0.data 1pf0.control 0 pf0.pull-up_enable table 24-5. atmega169a/169pa/329a/329pa/649a/649p boundary-scan order, 64-pin bit number signal name module 258 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 note: 1. private_signal1 should always be scanned in as zero. table 24-6. atmega3250a/3250pa/6450a/6450p boundary-scan order, 100-pin bit number signal name module 242 ac_idle comparator 241 aco 240 acme 239 ainbg 238 comp adc 237 aclk 236 acten 235 private_signal1 (1) 234 adcbgen 233 adcen 232 ampen 231 dac_9 230 dac_8 229 dac_7 228 dac_6 227 dac_5 226 dac_4 225 dac_3 224 dac_2 223 dac_1 222 dac_0 221 extch 220 gnden 219 hold 218 irefen 217 muxen_7 216 muxen_6 215 muxen_5 214 muxen_4 213 muxen_3 212 muxen_2 211 muxen_1 210 muxen_0 209 negsel_2 208 negsel_1 259 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 207 negsel_0 adc 206 passen 205 prech 204 st 203 vccren 202 pe0.data port e 201 pe0.control 200 pe0.pull-up_enable 199 pe1.data 198 pe1.control 197 pe1.pull-up_enable 196 pe2.data 195 pe2.control 194 pe2.pull-up_enable 193 pe3.data 192 pe3.control 191 pe3.pull-up_enable 190 pe4.data 189 pe4.control 188 pe4.pull-up_enable 187 pe5.data 186 pe5.control 185 pe5.pull-up_enable 184 pe6.data 183 pe6.control 182 pe6.pull-up_enable 181 pe7.data 180 pe7.control 179 pe7.pull-up_enable 178 pj0.data port j 177 pj0.control 176 pj0.pull-up_enable 175 pj1.data 174 pj1.control 173 pj1.pull-up_enable 172 pb0.data port b table 24-6. atmega3250a/3250pa/6450a/6450p boundary-scan order, 100-pin bit number signal name module 260 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 171 pb0.control port b 170 pb0.pull-up_enable 169 pb1.data 168 pb1.control 167 pb1.pull-up_enable 166 pb2.data 165 pb2.control 164 pb2.pull-up_enable 163 pb3.data 162 pb3.control 161 pb3.pull-up_enable 160 pb4.data 159 pb4.control 158 pb4.pull-up_enable 157 pb5.data 156 pb5.control 155 pb5.pull-up_enable 154 pb6.data 153 pb6.control 152 pb6.pull-up_enable 151 pb7.data 150 pb7.control 149 pb7.pull-up_enable 148 pg3.data port g 147 pg3.control 146 pg3.pull-up_enable 145 pg4.data 144 pg4.control 143 pg4.pull-up_enable 142 pg5 (observe only) 141 rstt reset logic (observe-only) 140 rsthv 139 extclken enable signals for main clock/oscillators 138 oscon 137 rcoscen 136 osc32en table 24-6. atmega3250a/3250pa/6450a/6450p boundary-scan order, 100-pin bit number signal name module 261 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 135 extclk (xtal1) clock input and oscillators for the main clock (observe-only) 134 oscck 133 rcck 132 osc32ck 131 pj2.data port j 130 pj2.control 129 pj2.pull-up_enable 128 pj3.data 127 pj3.control 126 pj3.pull-up_enable 125 pj4.data 124 pj4.control 123 pj4.pull-up_enable 122 pj5.data 121 pj5.control 120 pj5.pull-up_enable 119 pj6.data 118 pj6.control 117 pj6.pull-up_enable 116 pd0.data port d 115 pd0.control 114 pd0.pull-up_enable 113 pd1.data 112 pd1.control 111 pd1.pull-up_enable 110 pd2.data 109 pd2.control 108 pd2.pull-up_enable 107 pd3.data 106 pd3.control 105 pd3.pull-up_enable 104 pd4.data 103 pd4.control 102 pd4.pull-up_enable 101 pd5.data 100 pd5.control table 24-6. atmega3250a/3250pa/6450a/6450p boundary-scan order, 100-pin bit number signal name module 262 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 99 pd5.pull-up_enable 98 pd6.data 97 pd6.control 96 pd6.pull-up_enable 95 pd7.data 94 pd7.control 93 pd7.pull-up_enable 92 pg0.data port g 91 pg0.control 90 pg0.pull-up_enable 89 pg1.data 88 pg1.control 87 pg1.pull-up_enable 86 pc0.data port c 85 pc0.control 84 pc0.pull-up_enable 83 pc1.data 82 pc1.control 81 pc1.pull-up_enable 80 pc2.data 79 pc2.control 78 pc2.pull-up_enable 77 pc3.data 76 pc3.control 75 pc3.pull-up_enable 74 pc4.data 73 pc4.control 72 pc4.pull-up_enable 71 pc5.data 70 pc5.control 69 pc5.pull-up_enable 68 ph0.data port h 67 ph0.control 66 ph0.pull-up_enable 65 ph1.data 64 ph1.control table 24-6. atmega3250a/3250pa/6450a/6450p boundary-scan order, 100-pin bit number signal name module 263 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 63 ph1.pull-up_enable 62 ph2.data 61 ph2.control 60 ph2.pull-up_enable 59 ph3.data 58 ph3.control 57 ph3.pull-up_enable 56 pc6.data port c 55 pc6.control 54 pc6.pull-up_enable 53 pc7.data 52 pc7.control 51 pc7.pull-up_enable 50 pg2.data port g 49 pg2.control 48 pg2.pull-up_enable 47 pa7.data port a 46 pa7.control 45 pa7.pull-up_enable 44 pa6.data 43 pa6.control 42 pa6.pull-up_enable 41 pa5.data 40 pa5.control 39 pa5.pull-up_enable 38 pa4.data 37 pa4.control 36 pa4.pull-up_enable 35 pa3.data 34 pa3.control 33 pa3.pull-up_enable 32 pa2.data 31 pa2.control 30 pa2.pull-up_enable 29 pa1.data 28 pa1.control table 24-6. atmega3250a/3250pa/6450a/6450p boundary-scan order, 100-pin bit number signal name module 264 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 notes: 1. private_signal1 should always be scanned in as zero 24.7 boundary-scan description language files boundary-scan description language (bsdl) files describe boundary-scan capable devices in a standard format used by automated test-generation software. the order and function of bits in the boundary-scan data register are included in this description. a bsdl file for atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p is available. 27 pa1.pull-up_enable 26 pa0.data 25 pa0.control 24 pa0.pull-up_enable 23 ph4.data port h 22 ph4.control 21 ph4.pull-up_enable 20 ph5.data 19 ph5.control 18 ph5.pull-up_enable 17 ph6.data 16 ph6.control 15 ph6.pull-up_enable 14 ph7.data 13 ph7.control 12 ph7.pull-up_enable 11 pf3.data port f 10 pf3.control 9 pf3.pull-up_enable 8pf2.data 7 pf2.control 6 pf2.pull-up_enable 5pf1.data 4 pf1.control 3 pf1.pull-up_enable 2pf0.data 1 pf0.control 0 pf0.pull-up_enable table 24-6. atmega3250a/3250pa/6450a/6450p boundary-scan order, 100-pin bit number signal name module 265 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 24.8 boundary-scan related re gister in i/o memory 24.8.1 mcucr ? mcu control register the mcu control register contains control bits for general mcu functions. ? bit 7 ? jtd: jtag interface disable w hen this bit is zero, the jtag interface is enabl ed if the jtagen fuse is programmed. if this bit is one, the jtag interface is disabled. in or der to avoid unintentional disabling or enabling of the jtag interface, a timed sequence must be followed when changing this bit: the application software must write this bit to the desired value twice within four cycles to change its value. note that this bit must not be altered when using the on-chip debug system. if the jtag interface is left unconnected to ot her jtag circuitry, the jtd bit should be set to one. the reason for this is to avoid static current at the tdo pin in the jtag interface. 24.8.2 mcusr ? mcu status register the mcu status register provides information on which reset source caused an mcu reset. ? bit 4 ? jtrf: jtag reset flag this bit is set if a reset is being caused by a logic one in the jtag reset register selected by the jtag instruction avr_reset. this bit is rese t by a power-on reset, or by writing a logic zero to the flag. bit 76543210 0x35 (0x55) jtd - - pud ? ? ivsel ivce mcucr read/ w rite r/ w rrr/ w rrr/ w r/ w initial value 00000000 bit 76543210 0x34 (0x54) ? ? ?jtrf wdrf borf extrf porf mcusr read/ w rite rrrr/ w r/ w r/ w r/ w r/ w initial value 0 0 0 see bit description 266 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 25. boot loader support ? read -while-write self-programming 25.1 features ? read-while-write self-programming ? flexible boot memory size ? high security (separate boot lock bits for a flexible protection) ? separate fuse to select reset vector ? optimized page (1) size ? code efficient algorithm ? efficient read-modify-write support note: 1. a page is a section in the flash consisting of several bytes (see table 26-7 on page 286 ) used during programming. the page organization does not affect normal operation. 25.2 overview the boot loader support provides a real read- w hile- w rite self-programming mechanism for downloading and uploading program code by the m cu itself. this feature a llows flexible applica- tion software updates controlled by the mcu using a flash-resident boot loader program. the boot loader program can use any available data interface and associated protocol to read code and write (program) that code into the flash memory, or read the code from the program mem- ory. the program code within the boot loader section has the capability to write into the entire flash, including the boot loader memory. the b oot loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. the size of the boot loader memory is configurable with fuses and t he boot loader has two separate sets of boot lock bits which can be set indepen dently. this gives the user a uniq ue flexibility to select differ- ent levels of protection. 25.3 application and boot loader flash sections the flash memory is organized in two main sections, the application section and the boot loader section (see figure 25-2 on page 269 ). the size of the different sections is configured by the bootsz fuses as shown in table 25-6 on page 278 and figure 25-2 on page 269 . these two sections can have different level of protecti on since they have different sets of lock bits. 25.3.1 application section the application section is the section of the flash that is used for storing the application code. the protection level for the application section can be selected by the application boot lock bits (boot lock bits 0), see table 25-2 on page 270 . the application section can never store any boot loader code since the spm instruction is disabled when executed from the application section. 25.3.2 bls ? boot loader section w hile the application section is used for storing the application code, the the boot loader soft- ware must be located in the bls since the spm instruction can initiate a programming when executing from the bls only. the spm instruct ion can access the entire flash, including the bls itself. the protection level for the boot loader section can be selected by the boot loader lock bits (boot lock bits 1), see table 25-3 on page 270 . 267 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 25.4 read-while-write and no r ead-while-write flash sections w hether the cpu supports read- w hile- w rite or if the cpu is halted during a boot loader soft- ware update is dependent on which address that is being programmed. in addition to the two sections that are configurable by the bootsz fuses as described above, the flash is also divided into two fixed sections, the read- w hile- w rite (r ww ) section and the no read- w hile- w rite (nr ww ) section. the limit between the r ww - and nr ww sections is given in table 25- 7 on page 279 and figure 25-2 on page 269 . the main difference between the two sections is: ? w hen erasing or writing a page located inside the r ww section, the nr ww section can be read during the operation. ? w hen erasing or writing a page located inside the nr ww section, the cpu is halted during the entire operation. note that the user software can never read any code that is located inside the r ww section dur- ing a boot loader software operation. the syntax ?read- w hile- w rite section? refers to which section that is being programmed (erased or written), not which section that actually is being read during a boot loader software update. 25.4.1 rww ? read-while-write section if a boot loader software update is programming a page inside the r ww section, it is possible to read code from the flash, but only code that is located in the nr ww section. during an on- going programming, the software must ensure that the r ww section never is being read. if the user software is trying to read code that is located inside the r ww section (i.e., by a call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown state. to avoid this, the interrupts should either be disabled or moved to the boot loader sec- tion. the boot loader sectio n is always located in the nr ww section. the r ww section busy bit (r ww sb) in the store program me mory control and status re gister (spmcsr) will be read as logical one as long as the r ww section is blocked for reading. after a programming is com- pleted, the r ww sb must be cleared by software before reading code located in the r ww section. see ?spmcsr ? store program memory control and status register? on page 281. for details on how to clear r ww sb. 25.4.2 nrww ? no read-while-write section the code located in the nr ww section can be read when the boot loader software is updating a page in the r ww section. w hen the boot loader code updates the nr ww section, the cpu is halted during the entire page erase or page w rite operation. table 25-1. read- w hile- w rite features which section does the z-pointer address during the programming? which section can be read during programming? is the cpu halted? read-while-write supported? r ww section nr ww section no yes nr ww section none yes no 268 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 25-1. read- w hile- w rite vs. no read- w hile- w rite read-while-write (rww) s ection no read-while-write (nrww) s ection z-pointer addresses rww s ection z-pointer addresses nrww s ection cpu is halted during the operation code located in nrww s ection can be read during the operation 269 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 25-2. memory sections note: 1. the parameters in the figure above are given in table 25-6 on page 278 . 0x0000 flashend program memory bootsz = '11' application flash s ection boot loader flash s ection flashend program memory bootsz = '10' 0x0000 program memory bootsz = '01' program memory bootsz = '00' application flash s ection boot loader flash s ection 0x0000 flashend application flash s ection flashend end rww s tart nrww application flash s ection boot loader flash s ection boot loader flash s ection end rww s tart nrww end rww s tart nrww 0x0000 end rww, end application s tart nrww, s tart boot loader application flash s ection application flash s ection application flash s ection read-while-write s ection no read-while-write s ection read-while-write s ection no read-while-write s ection read-while-write s ection no read-while-write s ection read-while-write s ection no read-while-write s ection end application s tart boot loader end application s tart boot loader end application s tart boot loader 270 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 25.5 boot loader lock bits if no boot loader capability is n eeded, the entire flash is available for application code. the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique flexibility to sele ct different levels of protection. the user can select: ? to protect the entire flash from a software update by the mcu. ? to protect only the boot loader flash section from a software update by the mcu. ? to protect only the application flash section from a software update by the mcu. ? allow software update in the entire flash. see table 25-2 on page 270 and table 25-3 on page 270 for further details. the boot lock bits and general lock bits can be set in software and in serial or parallel programming mode, but they can be cleared by a chip erase command only. the general w rite lock (lock bit mode 2) does not control the programming of the flash memory by spm instruction. similarly, the gen- eral read/ w rite lock (lock bit mode 1) does not contro l reading nor writing by lpm/spm, if it is attempted. note: 1. ?1? means unprogrammed, ?0? means programmed note: 1. ?1? means unprogrammed, ?0? means programmed table 25-2. boot lock bit0 protection modes (application section) (1) blb0 mode blb02 blb01 protection 111 no restrictions for spm or lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the application section, and lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 401 lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. table 25-3. boot lock bit1 protection modes (boot loader section) (1) blb1 mode blb12 blb11 protection 111 no restrictions for spm or lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 401 lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 271 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 25.6 entering the b oot loader program entering the boot loader takes place by a jump or call from the application program. this may be initiated by a trigger such as a command received via usart, or spi interface. alternatively, the boot reset fuse can be programmed so that the reset vector is pointing to the boot flash start address after a reset. in this case, the boot loader is started after a reset. after the applica- tion code is loaded, the program can start execut ing the application code. note that the fuses cannot be changed by the mcu itself. this means that once the boot reset fuse is pro- grammed, the reset vector will always point to the boot loader reset and the fuse can only be changed through the serial or parallel programming interface. note: 1. ?1? means unprogrammed, ?0? means programmed table 25-4. boot reset fuse (1) bootrst reset address 1 reset vector = application reset (address 0x0000) 0 reset vector = boot loader reset (see table 25-6 on page 278 ) 272 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 25.7 addressing the flash during self-programming the z-pointer is used to address the spm commands. since the flash is organized in pages (see table 26-7 on page 286 ), the program counter can be treated as having two different sections. one sect ion, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. this is shown in figure 25-3 . note that the page erase and page w rite operations are addressed independently. therefore it is of major importance that the boot loader software addresses the same page in both the page erase and page w rite operation. once a program- ming operation is initiated, the address is latched and the z-pointer can be used for other operations. the only spm operation that does not use the z-pointer is setting the boot loader lock bits. the content of the z-pointer is ignored and will have no effect on the operation. the lpm instruction does also use the z-pointer to store the address. since this instruction addresses the flash byte-by-byte, also the lsb (bit z0) of the z-pointer is used. figure 25-3. addressing the flash during spm (1) note: 1. the different variables used in figure 25-3 are listed in table 25-8 on page 279 . 2. pcpage and pc w ord are listed in table 26-7 on page 286 . bit 151413121110 9 8 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30) z7z6z5z4z3z2z1z0 76543210 program memory 0 1 15 z - regi s ter bit 0 zpagem s b word addre ss within a page page addre ss within the fla s h zpcm s b in s truction word pag e pcword[pagem s b:0]: 00 01 02 pageend pag e pcword pcpage pcm s b pagem s b program counter 273 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 25.8 self-programming the flash the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page buffer, the page must be erased. the temporary page buf- fer is filled one word at a time using spm and the buffer can be filled either before the page erase command or between a page erase and a page w rite operation: alternative 1, fill the bu ffer before a page erase ? fill temporary page buffer ? perform a page erase ? perform a page w rite alternative 2, fill the bu ffer after page erase ? perform a page erase ? fill temporary page buffer ? perform a page w rite if only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. w hen using alternative 1, the boot loader provides an effective read-modify- w rite feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. if alter- native 2 is used, it is not possible to read the old data while loading since the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essential that the page address used in both the page erase and page w rite operation is addressing the same page. see ?boot loader: simple assembly code example? on page 277 for an assembly code example. 25.8.1 performing page erase by spm to execute page erase, set up the address in the z-pointer, write ?x0000011? to spmcsr and execute spm within four clock cycles after writing spmcsr. (1) the data in r1 and r0 is ignored. the page address must be written to pcpage in the z-register. other bits in the z-pointer will be ignored during this operation. ? page erase to the r ww section: the nr ww section can be read during the page erase. ? page erase to the nr ww section: the cpu is halted during the operation. note: 1. if an interrupt occurs in the timed sequence the four cycle access cannot be guaranteed. in order to ensure atomic operation you must di sable interrupts before writing to spmcsr. 25.8.2 filling the temporary buffer (page loading) to write an instruction word, set up the address in the z-pointer and data in r1:r0, write ?00000001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the content of pc w ord in the z-register is used to address the data in the temporary buffer. the temporary buffer will auto-erase after a page w rite operation or by writing the r ww sre bit in spmcsr. it is also erased after a system reset. note that it is not possible to write more than one time to each address without erasing the temporary buffer. if the eeprom is written in the middle of an spm page load operation, all data loaded will be lost. 274 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 25.8.3 performing a page write to execute page w rite, set up the address in the z-pointer, write ?x0000101? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage. other bits in the z-pointer must be written to zero during this operation. ? page w rite to the r ww section: the nr ww section can be read during the page w rite. ? page w rite to the nr ww section: the cpu is halted during the operation. 25.8.4 using the spm interrupt if the spm interrupt is en abled, the spm interrupt will genera te a constant in terrupt when the spmen bit in spmcsr is cleared. this means th at the interrupt can be used instead of polling the spmcsr register in software. w hen using the spm interrupt, the interrupt vectors should be moved to the bls section to avoid that an interrupt is accessing the r ww section when it is blocked for reading. how to move the interrupts is described in ?interrupts? on page 55 . 25.8.5 consideration while updating bls special care must be taken if the user allows the boot loader section to be updated by leaving boot lock bit11 unprogrammed. an accidental write to the boot loader itself can corrupt the entire boot loader, and further software updates might be impossible. if it is not necessary to change the boot loader software itself, it is recommended to program the boot lock bit11 to protect the boot loader software from any internal software changes. 25.8.6 prevent reading the rww section during self-programming during self-programming (either page erase or page w rite), the r ww section is always blocked for reading. the user software itself must prevent that this section is addressed during the self programming operation. the r ww sb in the spmcsr will be set as long as the r ww section is busy. during self-programming the interrupt vector table should be moved to the bls as described in ?interrupts? on page 55 , or the interrupts must be disabled. before addressing the r ww section after the programming is completed, the user software must clear the r ww sb by writing the r ww sre. see ?boot loader: simple assembly code example? on page 277 for an example. 25.8.7 setting the boot loader lock bits by spm to set the boot loader lock bits and general lock bits, write the desired data to r0, write ?x0001001? to spmcsr and execute spm within four clock cycles after writing spmcsr. see table 25-2 and table 25-3 for how the different settings of the boot loader bits affect the flash access. if bits 5...0 in r0 are clear ed (zero), the corresponding lock bit will be programmed if an spm instruction is exec uted within four cycles after blbset and spmen are set in spmcsr. the z- pointer is don?t care during this operation, but fo r future compatibility it is recommended to load the z-pointer with 0x0001 (s ame as used for reading the lock bi ts). for future compatibility it is also recommended to set bits 7 and 6 in r0 to ?1? when writing the lock bits. w hen program- ming the lock bits the entire flas h can be read during the operation. bit 76543210 r0 1 1 blb12 blb11 blb02 blb01 lb2 lb1 275 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 25.8.8 eeprom write prevents writing to spmcsr note that an eeprom write oper ation will block all software progra mming to flash. reading the fuses and lock bits from software will also be prevented during the eeprom write operation. it is recommended that the user checks the status bit (ee w e) in the eecr register and verifies that the bit is cleared before writing to the spmcsr register. 25.8.9 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from software. to read the lock bits, load the z-pointer with 0x0001 and set the blbset and spmen bits in spmcsr. w hen an lpm instruc- tion is executed within three cpu cycles after the blbset and spmen bits are set in spmcsr, the value of the lock bits will be loaded in the destination register. the blbset and spmen bits will auto-clear upon completion of reading the lo ck bits or if no lpm instruction is executed within three cpu cycles or no spm instruct ion is executed withi n four cpu cycles. w hen blb- set and spmen are cleared, lpm will work as described in the instruction set manual. the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fuse low byte, load the z-pointer with 0x0000 and set the blbset and spmen bits in spmcsr. w hen an lpm instruction is executed within three cycles after the blbset and spmen bits are set in the spmcsr, the value of the fuse low byte (flb) will be loaded in the destination register as shown below. refer to table 26-5 on page 285 for a detailed description and mapping of the fuse low byte. similarly, when reading the fuse high byte, load 0x0003 in the z-pointer. w hen an lpm instruc- tion is executed within three cycles after the blbset and spmen bits are set in the spmcsr, the value of the fuse high byte (fhb) will be load ed in the destination re gister as shown below. refer to table 26-4 on page 285 for detailed description and mapping of the fuse high byte. w hen reading the extended fuse byte, load 0x0002 in the z-pointer. w hen an lpm instruction is executed within three cycles after the blbs et and spmen bits are set in the spmcsr, the value of the extended fuse byte (efb) will be loaded in the desti nation register as shown below. refer to table 26-3 on page 284 for detailed description and mapping of the extended fuse byte. fuse and lock bits that are programmed, will be read as zero. fuse and lock bits that are unprogrammed, will be read as one. bit 76543210 rd ? ? blb12 blb11 blb02 blb01 lb2 lb1 bit 76543210 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 76543210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 bit 7 6 5 4 3 2 1 0 rd ? ? ? ? efb3efb2efb1efb0 276 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 25.8.10 preventing flash corruption during periods of low v cc , the flash program can be corrupted because the supply voltage is too low for the cpu and the flash to operate properly. these issues are the same as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by two situ ations when the voltage is too low. first, a regular write sequence to the flash requires a minimum voltage to operate correctly. secondly, the cpu itself can execute instruct ions incorrectly, if the supply voltage for executing instructions is too low. flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. if there is no need for a bo ot loader update in the system, program the boot loader lock bits to prevent any boot loader software updates. 2. keep the avr reset active (low) during peri ods of insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating volt- age matches the detection level. if not, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 3. keep the avr core in power-down sleep mode during periods of low v cc . this will pre- vent the cpu from attempting to decode and execute instructions, effectively protecting the spmcsr register and thus the flash from unintentional writes. 25.8.11 programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 25-5 shows the typical pro- gramming time for flash accesses from the cpu. table 25-5. spm programming time symbol min programming time max programming time flash write (page erase, page w rite, and write lock bits by spm) 3.7ms 4.5ms 277 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 25.8.12 boot loader: simple assembly code example ;-the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y pointer ; the first data location in flash is pointed to by the z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code inside nrww section can ; be read during self-programming (page erase and page write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-it is assumed that either the interrupt table is moved to the boot ; loader section or that the interrupts are disabled. .equ pagesizeb = pagesize*2 ;pagesizeb is page size in bytes, not words .org smallbootstart write_page: ; page erase ldi spmcrval, (1< 280 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 25.8.14 boot loader parameters (atmega325a/325pa/3250a/3250pa/625a/645p/6450a/6450p) in table 25-6 through table 25-8 , the parameters used in the description of the self-program- ming are given. note: 1. the different bootsz fuse configurations are shown in figure 25-2 note: 1. for details about these two section, see ?nr ww ? no read- w hile- w rite section? on page 267 and ?r ww ? read- w hile- w rite section? on page 267 . note: 1. z0: should be zero for all spm comm ands, byte select for the lpm instruction. see ?addressing the flash during self-programming? on page 272 for details about the use of z-pointer during self- programming. table 25-9. boot size configuration (1) (atmega325a/325pa/3250a/3250pa/625a/645p/6450a/6450p) bootsz1 bootsz0 boot size pages application flash section boot loader flash section end application section boot reset address (start boot loader section) 1 1 256/512 words 4 0x0000-0x3eff/ 0x0000-0x7dff 0x3f00-0x3fff/ 0x7e00-0x7fff 0x3eff/ 0x7dff 0x3f00/ 0x7e00 1 0 512/1024 words 8 0x0000-0x3dff/ 0x0000-0x7bff/ 0x3e00-0x3fff/ 0x7c00-0x7fff 0x3dff/ 0x7bff 0x3e00/ 0x7c00 0 1 1024/2048 words 16 0x0000-0x3bff/ 0x0000-0x77ff 0x3c00-0x3fff/ 0x7800-0x7fff 0x3bff/ 0x77ff 0x3c00/ 0x7800 0 0 2048/4096 words 32 0x0000-0x37ff/ 0x0000-0x6fff 0x3800-0x3fff/ 0x7000-0x7fff 0x37ff/ 0x6fff 0x3800/ 0x7000 table 25-10. read- w hile- w rite limit (1) atmega325a/325pa/3250a/3250pa/625a/645p/6450a/6450p) section pages address read- w hile- w rite section (r ww ) 224/224 0x0000 - x37ff/ 0x0000 - 0x6fff no read- w hile- w rite section (nr ww ) 32/32 0x3800 - 0x3fff/ 0x7000-0x7fff table 25-11. explanation of different variables used in figure 25-3 and the mapping to the z- pointer (1) (atmega325a/325pa/3250a/3250pa/625a/645p/6450a/6450p) variable corresponding z-value description pcmsb 13/14 most significant bit in the program coun ter. (program counter is 14/15 bits pc[13/14:0]) pagemsb 5/6 most significant bit which is used to address the words within one page (64/128 words in a page requires six/seven bits pc [5/6:0]). zpcmsb z14/15 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z6/7 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[13/14:6/ 7] z14/15:z7/8 program counter page address: page select, for page erase and page w rite pc w ord pc[5/6:0] z6/7:z1 program counter word address: w ord select, for filling temporary buffer (must be zero during page w rite operation) 281 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 25.9 register description 25.9.1 spmcsr ? store program memory control and status register the store program memory control and status register contains the control bits needed to con- trol the boot loader operations. ? bit 7 ? spmie: spm interrupt enable w hen the spmie bit is written to one, and the i-bit in the status register is set (one), the spm ready interrupt will be enabled. the spm ready in terrupt will be ex ecuted as long as the spmen bit in the spmcsr register is cleared. ? bit 6 ? rwwsb: read-while-write section busy w hen a self-programming (page erase or page w rite) operation to the r ww section is initi- ated, the r ww sb will be set (one) by hardware. w hen the r ww sb bit is set, the r ww section cannot be accessed. the r ww sb bit will be cleared if the r ww sre bit is written to one after a self-programming operation is completed. alternatively the r ww sb bit will automatically be cleared if a page load operation is initiated. ? bit 5 ? reserved this bit is reserved and will always read as zero. ? bit 4 ? rwwsre: read-while-write section read enable w hen programming (page erase or page w rite) to the r ww section, the r ww section is blocked for reading (the r ww sb will be set by hardware). to re-enable the r ww section, the user software must wait unt il the programming is complet ed (spmen will be cl eared). then, if the r ww sre bit is written to one at the same time as spmen, the next spm instruction within four clock cycles re-enables the r ww section. the r ww section cannot be re-enabled while the flash is busy with a page erase or a page w rite (spmen is set). if the r ww sre bit is writ- ten while the flash is being loaded, the flas h load operation will abort and the data loaded will be lost. ? bit 3 ? blbset: boot lock bit set if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles sets boot lock bits and general lock bits, according to the data in r0. the data in r1 and the address in the z-pointer are ignored. th e blbset bit will automatically be cleared upon completion of the lock bit set, or if no spm instruction is executed within four clock cycles. an lpm instruction within three cycles after blbset and spmen are set in the spmcsr reg- ister, will read either the lock bits or the fuse bits (depending on z0 in the z-pointer) into the destination register. see ?reading the fuse and lock bits from software? on page 275 for details. bit 7 65 4 3 210 0x37 (0x57) spmie rwwsb ? rwwsre blbset pgwrt pgers spmen spmcsr read/ w rite r/ w rrr/ w r/ w r/ w r/ w r/ w initial value 0 0 0 0 0 0 0 0 282 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 ? bit 2 ? pgwrt: page write if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page w rite, with the data stored in the temporary buffer. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pg w rt bit will auto-clear upon co mpletion of a page w rite, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire page w rite operation if the nr ww section is addressed. ? bit 1 ? pgers: page erase if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page erase. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgers bi t will auto-clear upon comp letion of a page erase, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire page w rite operation if the nr ww section is addressed. ? bit 0 ? spmen: store program memory enable this bit enables the spm instruction for the next four clock cycles. if written to one together with either r ww sre, blbset, pg w rt? or pgers, the following spm instruction will have a spe- cial meaning, see description abo ve. if only spmen is written, the following spm instruction will store the value in r1:r0 in the temporary page buffer addressed by the z-pointer. the lsb of the z-pointer is ignored. the spmen bit will aut o-clear upon completion of an spm instruction, or if no spm instruction is executed within four clock cycles. during page erase and page w rite, the spmen bit remains high until the operation is completed. w riting any other combination than ?10001?, ?01001?, ?00101?, ?00011? or ?00001? in the lower five bits will have no effect. 283 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 26. memory programming 26.1 program and data memory lock bits the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p provides six lock bits which can be left unprogrammed (?1?) or can be programmed (?0?) to obtain the addi- tional features listed in table 26-2 . the lock bits can only be erased to ?1? with the chip erase command. note: 1. ?1? means unprogrammed, ?0? means programmed table 26-1. lock bit byte (1) lock bit byte bit no description default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) blb12 5 boot lock bit 1 (unprogrammed) blb11 4 boot lock bit 1 (unprogrammed) blb02 3 boot lock bit 1 (unprogrammed) blb01 2 boot lock bit 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) table 26-2. lock bit protection modes (1)(2) memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 210 further programming of the flash and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode. (1) 300 further programming and verification of the flash and eeprom is disabled in parallel and serial programming mode. the boot lock bits and fuse bits are locked in both serial and parallel programming mode. (1) blb0 mode blb02 blb01 111 no restrictions for spm or lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the application section, and lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrup ts are disabled while executing from the application section. 401 lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 284 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed 26.2 fuse bits the atmega165a/165pa/325a/325pa/3250a/3 250pa/645a/645p/6450a/6450p has three fuse bytes. table 26-3 - table 26-5 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. note that the fuses are read as logical zero, ?0?, if they are programmed. notes: 1. see table 27-16 on page 327 for bodlevel fuse decoding. 2. port g, pg5 is input only. pull-up is always on. see ?alternate functions of port g? on page 84. blb1 mode blb12 blb11 111 no restrictions for spm or lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrup ts are disabled while executing from the boot loader section. 401 lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. table 26-2. lock bit protection modes (1)(2) (continued) memory lock bits protection type table 26-3. extended fuse byte fuse low byte bit no description default value ?7? 1 ?6? 1 ?5? 1 ?4? 1 bodlevel2 (1) 3 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (1) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel0 (1) 1 brown-out detector trigger level 1 (unprogrammed) rstdisbl (2) 0 external reset disable 1 (unprogrammed) 285 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 note: 1. the spien fuse is not accessible in serial programming mode. 2. the default value of bootsz1...0 results in maximum boot size. see table 25-6 on page 278 for details. 3. see ? w dtcr ? w atchdog timer control register? on page 53 for details. 4. never ship a product with the ocden fuse prog rammed regardless of the setting of lock bits and jtagen fuse. a programmed ocden fuse en ables some parts of the clock system to be running in all sleep modes. this may increase the power consumption. 5. if the jtag interface is left unconnected, the jt agen fuse should if possible be disabled. this to avoid static current at the tdo pin in the jtag interface. note: 1. the default value of sut1:0 results in maximum start-up time for the default clock source. see table 27-13 on page 326 for details. 2. the default setting of cksel3:0 result s in internal rc os cillator @ 8mhz. see table 8-10 on page 34 for details. 3. the ckout fuse allow the system cl ock to be output on porte7. see ?clock output buffer? on page 36 for details. 4. see ?system clock prescaler? on page 36 for details. the status of the fuse bits is not affected by chip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. table 26-4. fuse high byte fuse high byte bit no de scription default value ocden (4) 7 enable ocd 1 (unprogrammed, ocd disabled) jtagen (5) 6 enable jtag 0 (programmed, jtag enabled) spien (1) 5 enable serial program and data downloading 0 (programmed, spi prog. enabled) w dton (3) 4 w atchdog timer always on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed, eeprom not preserved) bootsz1 2 select boot size (see table 25-6 for details) 0 (programmed) (2) bootsz0 1 select boot size (see table 25-6 for details) 0 (programmed) (2) bootrst 0 select reset vector 1 (unprogrammed) table 26-5. fuse low byte fuse low byte bit no description default value ckdiv8 (4) 7 divide clock by 8 0 (programmed) ckout (3) 6 clock output 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (1) sut0 4 select start-up time 0 (programmed) (1) cksel3 3 select clock source 0 (programmed) (2) cksel2 2 select clock source 0 (programmed) (2) cksel1 1 select clock source 1 (unprogrammed) (2) cksel0 0 select clock source 0 (programmed) (2) 286 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 26.2.1 latching of fuses the fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves programming mode. this does not apply to the eesave fuse which will take effect once it is programmed. the fuse s are also latched on power-up in normal mode. 26.3 signature bytes all atmel microcontrollers have a three-byte signature code which identifies the device. this code can be read in both serial and parallel mode, also when the device is locked. the three bytes reside in a separate address space. the signature bytes are given in table 26-6 . 26.4 calibration byte the atmega165a/165pa/325a/325pa/3250a/ 3250pa/645a/645p/6450a/6450p has a byte calibration value for the internal rc oscillator. this byte resides in the high byte of address 0x000 in the signature address space. during reset, this byte is automatically written into the osccal register to ensure correct frequency of t he calibrated rc oscillator. 26.5 page size 26.6 parallel programming paramete rs, pin mapping, and commands this section describes how to parallel program and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p. pulses are assumed to be at least 250 ns unless otherwise noted. table 26-6. device and jtag id part signature bytes jtag 0x000 0x001 0x002 part number manufacture id atmega165a/165pa 0x1e 0x94 0x07 9407 0x1f atmega325a/325pa 0x1e 0x95 0x0d 950d 0x1f atmega3250a/3250pa 0x1e 0x95 0x0e 950e 0x1f atmega645a/645p 0x1e 0x96 0x0d 960d 0x1f atmega6450a/6450p 0x1e 0x96 0x0e 960e 0x1f table 26-7. no. of w ords in a page and no. of pages in the flash flash size page size pcword no. of pages pcpage pcmsb 8k words (16kbytes) 64 words pc[5:0] 128 pc[12:6] 12 table 26-8. no. of w ords in a page and no . of pages in the eeprom eeprom size page size pcword no. of pages pcpage eeamsb 512bytes 4 bytes eea[1:0] 128 eea[8:2] 8 287 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 26.6.1 signal names in this section, some pins of the atmega165a/165pa/325a/325pa/3250a/3250pa/6 45a/645p/6450a/6450p are referenced by signal names describing their functio nality during parallel programming, see figure 26-1 and table 26-9 . pins not described in the following table are referenced by pin names. the xa1/xa0 pins determine the action executed when the xtal1 pin is given a positive pulse. the bit coding is shown in table 26-11 . w hen pulsing w r or oe , the command loaded determines the action executed. the different commands are shown in table 26-12 . figure 26-1. parallel programming table 26-9. pin name mapping signal name in programming mode pi n name i/o function rdy/bsy pd1 o 0: device is busy programming, 1: device is ready for new command oe pd2 i output enable (active low) w r pd3 i w rite pulse (active low). bs1 pd4 i byte select 1 (?0? selects low byte, ?1? selects high byte) xa0 pd5 i xtal action bit 0 xa1 pd6 i xtal action bit 1 pagel pd7 i program memory and eeprom data page load bs2 pa0 i byte select 2 (?0? select s low byte, ?1? selects 2 nd high byte) data pb7-0 i/o bi-directional data bus (output when oe is low). vcc +5v gnd xtal1 pd1 pd2 pd 3 pd4 pd5 pd6 pb7 - pb0 data re s et pd7 +12 v b s 1 xa0 xa1 oe rdy/b s y pagel pa0 wr b s 2 avcc +5v 288 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 table 26-10. pin values used to enter programming mode pin symbol value pagel prog_enable[3] 0 xa1 prog_enable[2] 0 xa0 prog_enable[1] 0 bs1 prog_enable[0] 0 table 26-11. xa1 and xa0 coding xa1 xa0 action when xtal1 is pulsed 00 load flash or eeprom address (high or low address byte determined by bs1). 0 1 load data (high or low data byte for flash determined by bs1). 1 0 load command 1 1 no action, idle table 26-12. command byte bit coding command byte command executed 1000 0000 chip erase 0100 0000 w rite fuse bits 0010 0000 w rite lock bits 0001 0000 w rite flash 0001 0001 w rite eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom 289 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 26.7 parallel programming 26.7.1 enter programming mode the following algorithm puts the devi ce in parallel programming mode: 1. apply 4.5 - 5.5v between v cc and gnd. 2. set reset to ?0? and toggle xtal1 at least six times. 3. set the prog_enable pins listed in table 26-10 on page 288 to ?0000? and wait at least 100 ns. 4. apply 11.5 - 12.5v to reset . any activity on prog_enable pins within 100 ns after +12v has been applied to reset , will cause the device to fail entering programming mode. 5. w ait at least 50 s before sending a new command. 26.7.2 considerations for efficient programming the loaded command and address are retained in the device during programming. for efficient programming, the following should be considered. ? the command needs only be loaded once when writing or reading multiple memory locations. ? skip writing the data value 0xff, that is the contents of the entire eeprom (unless the eesave fuse is programmed) and flash after a chip erase. ? address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte eeprom. this consideration also applies to signature bytes reading. 26.7.3 chip erase the chip erase will erase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are not changed. a chip erase must be perfor med before the flas h and/or eeprom are reprogrammed. note: 1. the eeprpom memory is preserved duri ng chip erase if the eesave fuse is programmed. load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the command. 5. give w r a negative pulse. this starts the chip erase. rdy/bsy goes low. 6. w ait until rdy/bsy goes high before loading a new command. 26.7.4 programming the flash the flash is organized in pages, see table 26-7 on page 286 . w hen programming the flash, the program data is latched into a page buffer. this allows one page of program data to be pro- grammed simultaneously. the following procedure describes how to program the entire flash memory: 290 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 a. load command ? w rite flash? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for w rite flash. 4. give xtal1 a positive pulse. this loads the command. b. load address low byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?0?. this selects low address. 3. set data = address low byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address low byte. c. load data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte (0x00 - 0xff). 3. give xtal1 a positive pulse. this loads the data byte. d. load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the data byte. e. latch data 1. set bs1 to ?1?. this selects high data byte. 2. give pagel a positive pulse. this latches the data bytes. (see figure 26-3 for signal waveforms) f. repeat b through e until the entire buffer is filled or until all data within the page is loaded. w hile the lower bits in the address are mapped to words within the page, the higher bits address the pages within the flash . this is illustrated in figure 26-2 on page 291 . note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page w rite. g. load address high byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?1?. this selects high address. 3. set data = address high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. 291 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 h. program page 1. give w r a negative pulse. this starts programming of the entire page of data. rdy/bsy goes low. 2. w ait until rdy/bsy goes high (see figure 26-3 for signal waveforms). i. repeat b through h until the entire flash is programmed or until all data has been programmed. j. end page programming 1. 1. set xa1, xa0 to ?10?. this enables command loading. 2. set data to ?0000 0000?. this is the command for no operation. 3. give xtal1 a positive pulse. this loads the command, and the internal write signals are reset. figure 26-2. addressing the flash w hich is organized in pages (1) note: 1. pcpage and pc w ord are listed in table 26-7 on page 286 . program memory word addre ss within a page page addre ss within the fla s h in s truction word pag e pcword[pagem s b:0]: 00 01 02 pageend pag e pcword pcpage pcm s b pagem s b program counter 292 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 26-3. programming the flash w aveforms (1) note: 1. ?xx? is don?t care. the letters re fer to the programming description above. rdy/b s y wr oe re s et +12v pagel b s 2 0x10 addr. low addr. high data data low data high addr. low data low data high xa1 xa0 b s 1 xtal1 xx xx xx abcdeb cdegh f 293 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 26.7.5 programming the eeprom the eeprom is organized in pages, see table 26-8 on page 286 . w hen programming the eeprom, the program data is latche d into a page buffer. this al lows one page of data to be programmed simultaneously. th e programming algorithm for th e eeprom data memory is as follows (refer to ?programming the flash? on page 289 for details on command, address and data loading): 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). 5. e: latch data (give pagel a positive pulse). 6. k: repeat 3 through 5 until the entire buffer is filled. 7. l: program eeprom page 1.set bs to ?0?. 2.give w r a negative pulse. this starts prog ramming of the eeprom page. rdy/bsy goes low. 3. w ait until to rdy/bsy goes high before programming the next page (see figure 26-4 on page 293 for signal waveforms). figure 26-4. programming the eeprom w aveforms 26.7.6 reading the flash the algorithm for reading the flash memory is as follows (refer to ?programming the flash? on page 289 for details on command and address loading): 1. a: load command ?0000 0010?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. 5. set bs to ?1?. the flash word high byte can now be read at data. 6. set oe to ?1?. rdy/b s y wr oe re s et +12v pagel b s 2 0x11 addr. high data addr. low data addr. low data xx xa1 xa0 b s 1 xtal1 xx agbceb c el k 294 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 26.7.7 reading the eeprom the algorithm for reading the eeprom memory is as follows (refer to ?programming the flash? on page 289 for details on command and address loading): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the eeprom data byte can now be read at data. 5. set oe to ?1?. 26.7.8 programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to ?programming the flash? on page 289 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. give w r a negative pulse and wait for rdy/bsy to go high. 26.7.9 programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to ?programming the flash? on page 289 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 to ?1? and bs2 to ?0?. this selects high fuse byte. 4. give w r a negative pulse and wait for rdy/bsy to go high. 5. set bs1 to ?0?. this selects low data byte. 26.7.10 programming the extended fuse bits the algorithm for programming the extended fuse bits is as follows (refer to ?programming the flash? on page 289 for details on command and data loading): 1. 1. a: load command ?0100 0000?. 2. 2. c: load data byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. 3. set bs1 to ?0? and bs2 to ?1?. this selects extended fuse byte. 4. 4. give w r a negative pulse and wait for rdy/bsy to go high. 5. 5. set bs2 to ?0?. this selects low data byte. 295 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 26-5. programming the fuses w aveforms 26.7.11 programming the lock bits the algorithm for programming the lock bits is as follows (refer to ?programming the flash? on page 289 for details on command and data loading): 1. a: load command ?0010 0000?. 2. c: load data low byte. bit n = ?0? programs the lock bit. if lb mode 3 is programmed (lb1 and lb2 is programmed), it is not possible to program the boot lock bits by any external programming mode. 3. give w r a negative pulse and wait for rdy/bsy to go high. the lock bits can only be cleared by executing chip erase. 26.7.12 reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ?programming the flash? on page 289 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, bs2 to ?0? and bs1 to ?0?. the status of the fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, bs2 to ?1? and bs1 to ?1?. the status of the fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, bs2 to ?1?, and bs1 to ?0?. the status of the extended fuse bits can now be read at data (?0? means programmed). 5. set oe to ?0?, bs2 to ?0? and bs1 to ?1?. the status of the lock bits can now be read at data (?0? means programmed). 6. set oe to ?1?. rdy/bsy w r oe reset +12v pagel 0x40 data data xx xa1 xa0 bs1 xtal1 ac 0x40 data xx ac w rite fuse low byte w rite fuse high byte 0x40 data xx ac w rite extended fuse byte bs2 296 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 26-6. mapping between bs1, bs2 and the fuse and lock bits during read 26.7.13 reading the signature bytes the algorithm for reading the signatur e bytes is as follows (refer to ?programming the flash? on page 289 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 - 0x02). 3. set oe to ?0?, and bs to ?0?. the selected signature byte can now be read at data. 4. set oe to ?1?. 26.7.14 reading the calibration byte the algorithm for reading the calibration byte is as follows (refer to ?programming the flash? on page 289 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can now be read at data. 4. set oe to ?1?. 26.7.15 parallel programming characteristics figure 26-7. parallel programming timing, including some general timing requirements lock bits 0 1 b s 2 fuse high byte 0 1 b s 1 data fuse low byte 0 1 b s 2 extended fuse byte data & contol (data, xa0/1, b s 1, b s 2) xtal1 t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rdy/b s y pagel t phpl t plbx t bvph t xlwl t wlbx t bvwl wlrl 297 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 26-8. parallel programming timing, loading sequence with timing requirements (1) note: 1. the timing requirements shown in figure 26-7 (i.e., t dvxh , t xhxl , and t xldx ) also apply to load- ing operation. figure 26-9. parallel programming timing, reading sequence (within the same page) with timing requirements (1) note: 1. the timing requirements shown in figure 26-7 (i.e., t dvxh , t xhxl , and t xldx ) also apply to read- ing operation. table 26-13. parallel programming characteristics, v cc = 5v 10% symbol parameter min typ max units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 a t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 low to xtal1 high 200 ns t xhxl xtal1 pulse w idth high 150 ns t xldx data and control hold after xtal1 low 67 ns t xl w l xtal1 low to w r low 0 ns xtal1 pagel t plxh xlxh t t xlph addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data b s 1 xa0 xa1 load addre ss (low byte) load data (low byte) load data (high byte) load data load addre ss (low byte) xtal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data b s 1 xa0 xa1 load addre ss (low byte) read data (low byte) read data (high byte) load addre ss (low byte) t bvdv t oldv t xlol t ohdz 298 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 notes: 1. t w lrh is valid for the w rite flash, w rite eeprom, w rite fuse bits and w rite lock bits commands. 2. t w lrh_ce is valid for the chip erase command. 26.8 serial downloading both the flash and eeprom memo ry arrays can be programmed using the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (out- put). after reset is set low, the programming enable instruction needs to be executed first before program/erase operations can be executed. note, in table 26-14 on page 298 , the pin mapping for spi programming is listed. not all pa rts use the spi pins dedicated for the internal spi interface. 26.8.1 serial programming pin mapping t xlph xtal1 low to pagel high 0 ns t plxh pagel low to xtal1 high 150 ns t bvph bs1 valid before pagel high 67 ns t phpl pagel pulse w idth high 150 ns t plbx bs1 hold after pagel low 67 ns t w lbx bs2/1 hold after w r low 67 ns t pl w l pag e l l o w t o w r low 67 ns t bv w l bs1 valid to w r low 67 ns t w l w h w r pulse w idth low 150 ns t w lrl w r low to rdy/bsy low 0 1 s t w lrh w r low to rdy/bsy high (1) 3.7 4.5 ms t w lrh_ce w r low to rdy/bsy high for chip erase (2) 7.5 9 ms t xlol xtal1 low to oe low 0 ns t bvdv bs1 valid to data valid 0 250 ns t oldv oe low to data valid 250 ns t ohdz oe high to data tri-stated 250 ns table 26-13. parallel programming characteristics, v cc = 5v 10% (continued) symbol parameter min typ max units table 26-14. pin mapping serial programming symbol pins i/o description mosi pb2 i serial data in miso pb3 o serial data out sck pb1 i serial clock 299 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 26-10. serial programming and verify (1) notes: 1. if the device is clocked by the internal oscilla tor, it is no need to connect a clock source to the xtal1 pin. 2. v cc - 0.3v < avcc < v cc + 0.3v, however, avcc should always be within 1.8 - 5.5v w hen programming the eeprom, an auto-erase cycle is built into the self-timed programming operation (in the serial mode only) and there is no need to first execute the chip erase instruction. the chip erase operation turns the content of every memory location in both the program and eeprom arrays into 0xff. depending on cksel fuses, a valid clock must be present. the minimum low and high periods for the serial clock (sck) input are defined as follows: low: > 2 cpu clock cycles for f ck < 12mhz, 3 cpu clock cycles for f ck >= 12mhz high: > 2 cpu clock cycles for f ck < 12mhz, 3 cpu clock cycles for f ck >= 12mhz 26.8.2 serial programming algorithm w hen writing serial data to the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p, data is clocked on the rising edge of sck. w hen reading data from the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p, data is clocked on the falling edge of sck. see figure 26-11 for timing details. to program and verify the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p in the serial pro- gramming mode, the following sequence is recommended (see four byte instruction formats in table 26-16 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in some sys- tems, the programmer can not guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse of at least two cpu clock cycles duration after sck has been set to ?0?. 2. w ait for at least 20ms and enable serial programming by sending the programming enable serial instruction to pin mosi. 3. the serial programming instru ctions will not work if the co mmunication is out of synchro- nization. w hen in sync. the second byte (0x53) , will echo back when issuing the third byte of the programming enable instruction. w hether the echo is correct or not, all four vcc gnd xtal1 sck miso mosi reset +1.8 - 5.5v avcc +1.8 - 5.5v (2) 300 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 bytes of the instruction must be transmitte d. if the 0x53 did no t echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time. the page size is found in table 26-7 on page 286 . the memory page is loaded one byte at a time by supplying the 6 lsb of the address and data together with the load program memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. the program memory page is stored by loading the w rite program memory page inst ruction with the 7 msb of the address. if polling ( rdy/bsy ) is not used, the user must wait at least t w d_flash before issuing the next page. (see table 26-15 .) accessing the serial programming interface before the flash write operation completes can result in incorrect programming. 5. a: the eeprom array is programmed one byte at a time by supplying the address and data together with the appropriate w rite instruction. an eeprom memory location is first automatically erased before ne w data is written. if polling ( rdy/bsy ) is not used, the user must wait at least t w d_eeprom before issuing the next byte (see table 26-15 ). in a chip erased device, no 0xffs in the data file(s) need to be programmed. b: the eeprom array is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 2 lsb of the address and data together with the load eeprom memory page instruction. the eeprom memory page is stored by loading the w rite eeprom memory page instructio n with the 4 msb of the address. w hen using eeprom page access on ly byte locations loaded with the load eeprom memory page instruction is altered. the remaining locations remain unchanged. if polling ( rdy/bsy ) is not used, the user must wait at least t w d_eeprom before issuing the next page (see table 26-15 ). in a chip erased device, no 0xff in the data file(s) need to be programmed. 6. any memory location can be verified by using the read instruction which returns the con- tent at the selected address at serial output miso. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. tu r n v cc power off table 26-15. minimum w ait delay before w riting the next flas h or eeprom location symbol minimum wait delay t w d_fuse 4.5ms t w d_flash 4.5ms t w d_eeprom 3.6ms t w d_erase 9.0ms 301 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 26-11. serial programming w aveforms m s b m s b l s b l s b s erial clock input ( s ck) s erial data input (mo s i) (mi s o) s ample s erial data output 302 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 26.8.3 serial programming instruction set table 26-16 and figure 26-12 on page 303 describes the instruction set. notes: 1. not all instructions are applicable for all parts 2. a = address 3. bits are programmed ?0?, unprogrammed ?1?. 4. to ensure future compatibility, unused fuses and lock bits should be unprogrammed (?1?). 5. refer to the corresponding section for fuse and lock bits, calibration and signature bytes and page size. 6. instructions accessing program memory use a word address. this address may be random within the page range. 7. see htt://www.atmel.com/avr for application notes regarding programming and programmers. if the lsb in rdy/bsy data byte out is ?1?, a programming operation is still pending. w ait until this bit returns ?0? before the ne xt instruction is carried out. table 26-16. serial programming instruction set instruction/operation instruction format byte 1 byte 2 byte 3 byte4 programming enable $ac $53 $00 $00 chip erase (program memory/eeprom) $ac $80 $00 $00 poll rdy/bsy $f0 $00 $00 data byte out load instructions load extended address byte (1) $4d $00 extended adr $00 load program memory page, high byte $48 $00 adr lsb high data byte in load program memory page, low byte $40 $00 adr lsb low data byte in load eeprom memory page (page access) $c1 $00 0000 00aa data byte in read instructions read program memory, high byte $28 adr msb adr lsb high data byte out read program memory, low byte $20 adr msb adr lsb low data byte out read eeprom memory $a0 0000 00aa aaaa aaaa data byte out read lock bits $58 $00 $00 data byte out read signature byte $30 $00 0000 00aa data byte out read fuse bits $50 $00 $00 data byte out read fuse high bits $58 $08 $00 data byte out read extended fuse bits $50 $08 $00 data byte out read calibration byte $38 $00 $00 data byte out write instructions (6) w rite program memory page $4c adr msb adr lsb $00 w rite eeprom memory $c0 0000 00aa aaaa aaaa data byte in w rite eeprom memory page (page access) $c2 0000 00aa aaaa aa00 $00 w rite lock bits $ac $e0 $00 data byte in w rite fuse bits $ac $a0 $00 data byte in w rite fuse high bits $ac $a8 $00 data byte in w rite extended fuse bits $ac $a4 $00 data byte in 303 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 w ithin the same page, the low data byte must be loaded prior to the high data byte. after data is loaded to the page buffer, program the eeprom page, see figure 26-12 . figure 26-12. serial programming instruction example 26.8.4 spi serial programming characteristics for characteristics of the spi module see ?spi timing characteristics? on page 328. byte 1 byte 2 byte 3 byte 4 adr lsb bit 15 b 0 s erial programming instruction program memory/ eeprom memory page 0 page 1 page 2 page n-1 page buffer write program memory page/ write eeprom memory page load program memory page (high/low byte)/ load eeprom memory page (page access) byte 1 byte 2 byte 3 byte 4 bit 15 b 0 adr msb page offset page number ad r m m s s b a a adr r l l s b b 304 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 26.9 programming via the jtag interface programming through the jtag interface requires control of the four jtag specific pins: tck, tms, tdi, and tdo. control of the reset and clock pins is not required. to be able to use the jtag interface, the jtagen fuse must be programmed. the device is default shipped with the fuse programmed. in addition, the jtd bit in mcucsr must be cleared. alternatively, if the jtd bit is set, the external reset can be fo rced low. then, the jtd bit will be cleared after two chip clocks, and the jtag pins are available for programming. this provides a means of using the jtag pins as normal port pi ns in running mode while still allowing in-sys- tem programming via the jtag interface. note th at this technique can not be used when using the jtag pins for boundary-scan or on-chip debug. in these cases the jtag pins must be ded- icated for this purpose. during programming the clock frequency of the tck input must be less than the maximum fre- quency of the chip. the system clock prescaler can not be used to divide the tck clock input into a sufficiently low frequency. as a definition in this datasheet, the lsb is shifted in and out first of all shift registers. 26.9.1 programming specific jtag instructions the instruction register is 4-bit wide, supporting up to 16 instructions. the jtag instructions useful for programming are listed below. the opcode for each instruction is shown behind the instruction name in hex format. the text describes which data register is selected as path between tdi and tdo for each instruction. the run-test/idle state of the tap controller is used to generate internal clocks. it can also be used as an idle state between jtag sequences . the state machine sequence for changing the instruction word is shown in figure 26-13 on page 305 . 305 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 26-13. state machine sequence for changing the instruction w ord 26.9.2 avr_reset (0xc) the avr specific public jtag in struction for setting the avr device in the reset mode or taking the device out from the reset mode. the tap controller is not reset by this instruction. the one bit reset register is selected as data register. no te that the reset will be active as long as there is a logic ?one? in the reset chain. the output from this chain is not latched. the active states are: ? shift-dr: the reset register is shifted by the tck input. 26.9.3 prog_enable (0x4) the avr specific public jtag instruction for enabling programming via the jtag port. the 16- bit programming enable register is selected as data register. the active states are the following: ? shift-dr: the programming enable signature is shifted into the data register. ? update-dr: the programming enable signature is compared to the correct value, and programming mode is entered if the signature is valid. test-logic-reset run-test/idle s hift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 306 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 26.9.4 prog_commands (0x5) the avr specific public jtag instruction for entering programming commands via the jtag port. the 15-bit programming command register is selected as data register. the active states are the following: ? capture-dr: the result of the previous command is loaded into the data register. ? shift-dr: the data register is shifted by the tck input, shifting out the result of the previous command and shifting in the new command. ? update-dr: the programming command is applied to the flash inputs ? run-test/idle: one clock cycle is generated, executing the applied command (not always required, see table 26-17 below). 26.9.5 prog_pageload (0x6) the avr specific public jtag instruction to directly load the flash data page via the jtag port. an 8-bit flash data byte register is selected as the data register. this is physically the 8 lsbs of the programming command register. the active states are the following: ? shift-dr: the flash data byte register is shifted by the tck input. ? update-dr: the content of the flash data byte register is copied into a temporary register. a write sequence is initiated that within 11 tck cycles loads the content of the temporary register into the flash page buffer. the avr automatically alternates between writing the low and the high byte for each new update-dr state, starting with the low byte for the first update- dr encountered after entering the prog_pageload command. the program counter is pre-incremented before writing the low byte, except for the first written byte. this ensures that the first data is written to the address se t up by prog_commands, and loading the last location in the page buffer does not make the program counter increment into the next page. 26.9.6 prog_pageread (0x7) the avr specific public jtag instruction to dire ctly capture the flash content via the jtag port. an 8-bit flash data byte register is selected as the data register. this is physically the 8 lsbs of the programming command register. the active states are the following: ? capture-dr: the content of the selected flash byte is captured into the flash data byte register. the avr automatically alternates between reading the low and the high byte for each new capture-dr state, starting with the low byte for the first capture-dr encountered after entering the prog_pageread command. the program counter is post-incremented after reading each high byte, including the first read byte. this ensures that the first data is captured from the first address set up by prog_commands, and reading the last location in the page makes the program counter increment into the next page. ? shift-dr: the flash data byte register is shifted by the tck input. 307 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 26.9.7 data registers the data registers are selected by the jtag instruction registers described in section ?pro- gramming specific jtag instructions? on page 304 . the data registers relevant for programming operations are: ? reset register ? programming enable register ? programming command register ? flash data byte register 26.9.8 reset register the reset register is a test data register used to reset the part during programming. it is required to reset the part before entering programming mode. a high value in the reset register corresponds to pulling the external reset low. the part is reset as long as there is a high value present in t he reset register. depending on the fuse settings for the clock options, the part will remain reset for a re set time-out period (refer to ?clock sources? on page 30 ) after releasing the reset register. the output from this data register is not latched, so the reset will take place immediately, as shown in figure 24-2 on page 241 . 26.9.9 programming enable register the programming enable register is a 16-bit regist er. the contents of this register is compared to the programming enable signature, binary code 0b1010_0011_0111_0000. w hen the con- tents of the register is equal to the programming enable signature, programming via the jtag port is enabled. the register is reset to 0 on power-on reset, and should always be reset when leaving programming mode. figure 26-14. programming enable register 26.9.10 programming command register the programming command register is a 15-bit regist er. this register is us ed to serially shift in programming commands, and to serially shift out the result of the previous command, if any. the jtag programming instruction set is shown in table 26-17 . the state sequence when shifting in the programming comma nds is illustrated in figure 26-16 . tdi tdo d a t a = dq clockdr & prog_enable programming enable 0xa 3 70 308 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 26-15. programming command register tdi tdo s t r o b e s a d d r e s s / d a t a flash eeprom fuses lock bits 309 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 table 26-17. jtag programming instruction set a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence tdo sequence notes 1a. chip erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. poll for chip erase complete 0110011_10000000 xxxxx o x_xxxxxxxx (2) 2a. enter flash w rite 0100011_00010000 xxxxxxx_xxxxxxxx 2b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (9) 2c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 2d. load data low byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx 2e. load data high byte 0010111_ iiiiiiii xxxxxxx_xxxxxxxx 2f. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2g. w rite flash page 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2h. poll for page w rite complete 0110111_00000000 xxxxx o x_xxxxxxxx (2) 3a. enter flash read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (9) 3c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 3d. read data low and high byte 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo xxxxxxx_ oooooooo low byte high byte 4a. enter eeprom w rite 0100011_00010001 xxxxxxx_xxxxxxxx 4b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (9) 4c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 4d. load data byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx 4e. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 4f. w rite eeprom page 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 4g. poll for page w rite complete 0110011_00000000 xxxxx o x_xxxxxxxx (2) 5a. enter eeprom read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (9) 310 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 5c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 5d. read data byte 0110011_ bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 6a. enter fuse w rite 0100011_01000000 xxxxxxx_xxxxxxxx 6b. load data low byte (6) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3) 6c. w rite fuse extended byte 0111011_00000000 0111001_00000000 0111011_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6d. poll for fuse w rite complete 0110111_00000000 xxxxx o x_xxxxxxxx (2) 6e. load data low byte (7) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3) 6f. w rite fuse high byte 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6g. poll for fuse w rite complete 0110111_00000000 xxxxx o x_xxxxxxxx (2) 6h. load data low byte (7) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3) 6i. w rite fuse low byte 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6j. poll for fuse w rite complete 0110011_00000000 xxxxx o x_xxxxxxxx (2) 7a. enter lock bit w rite 0100011_00100000 xxxxxxx_xxxxxxxx 7b. load data byte (9) 0010011_11 iiiiii xxxxxxx_xxxxxxxx (4) 7c. w rite lock bits 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 7d. poll for lock bit w rite complete 0110011_00000000 xxxxx o x_xxxxxxxx (2) 8a. enter fuse/lock bit read 0100011_00000100 xxxxxxx_xxxxxxxx 8b. read extended fuse byte (6) 0111010_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8c. read fuse high byte (7) 0111110_00000000 0111111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8d. read fuse low byte (8) 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8e. read lock bits (9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xx oooooo (5) table 26-17. jtag programming instruction (continued) set (continued) a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x instruction tdi sequence tdo sequence notes 311 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 notes: 1. this command sequence is not required if the seven msb are correctly set by the previous command sequence (which is normally the case). 2. repeat until o = ?1?. 3. set bits to ?0? to program the corresponding fuse, ?1? to unprogram the fuse. 4. set bits to ?0? to program the corresponding lock bit, ?1? to leave the lock bit unchanged. 5. ?0? = programmed, ?1? = unprogrammed. 6. the bit mapping for fuses extended byte is listed in table 26-3 on page 284 7. the bit mapping for fuses high byte is listed in table 26-4 on page 285 8. the bit mapping for fuses low byte is listed in table 26-5 on page 285 9. the bit mapping for lock bits byte is listed in table 26-1 on page 283 10. address bits exceeding pcmsb and eeamsb ( table 26-7 and table 26-8 ) are don?t care 11. all tdi and tdo sequences are represented by binary digits (0b...). 8f. read fuses and lock bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo xxxxxxx_ oooooooo xxxxxxx_ oooooooo xxxxxxx_ oooooooo (5) fuse ext. byte fuse high byte fuse low byte lock bits 9a. enter signature byte read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. load address byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 9c. read signature byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 10a. enter calibration byte read 0100011_00001000 xxxxxxx_xxxxxxxx 10b. load address byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 10c. read calibration byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 11a. load no operation command 0100011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx table 26-17. jtag programming instruction (continued) set (continued) a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x instruction tdi sequence tdo sequence notes 312 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 26-16. state machine sequence for changing/reading the data w ord 26.9.11 flash data byte register the flash data byte register provides an ef ficient way to load the entire flash page buffer before executing page w rite, or to read out/verify the content of the flash. a state machine sets up the control signals to the flash and senses the strobe signals from the flash, thus only the data words need to be shifted in/out. the flash data byte register actually consists of the 8-bit scan chain and a 8-bit temporary reg- ister. during page load, the update-dr state copies the content of the scan chain over to the temporary register and initiates a write sequence that within 11 tck cycles loads the content of the temporary register into the flash page bu ffer. the avr automatically alternates between writing the low and the high byte for each new update-dr state, starting with the low byte for the first update-dr encountered after entering the prog_pageload command. the program counter is pre-incremented before writing the low byte, except for the first written byte. this ensures that the first data is written to the address set up by prog_commands, and loading the last location in the page buffer does not make the program counter increment into the next page. during page read, the content of the selected flash byte is captured into the flash data byte register during the capture-dr state. the avr automatically alternates between reading the low and the high byte for each new capture-dr state, starting with the low byte for the first cap- test-logic-reset run-test/idle shift-dr exit1-dr pause-dr exit2-dr update-dr s elect-ir s can capture-ir s hift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 313 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 ture-dr encountered after entering the prog_pageread command. the program counter is post-incremented after reading each high byte, including the first read byte. this ensures that the first data is captured from the first ad dress set up by prog_commands, and reading the last location in the page makes the program counter increment into the next page. figure 26-17. flash data byte register the state machine controlling the flash data by te register is clocked by tck. during normal operation in which eight bits are shifted for eac h flash byte, the clock cycles needed to navigate through the tap controller automatically feeds the state machine for the flash data byte regis- ter with sufficient number of clock pulses to complete its operation transparently for the user. however, if too few bits are shifted between each update-dr state during page load, the tap controller should stay in the run-test/idle state for some tck cycles to ensure that there are at least 11 tck cycles between each update-dr state. 26.9.12 programming algorithm all references below of type ?1a?, ?1b?, and so on, refer to table 26-17 on page 309 . 26.9.13 entering programming mode 1. enter jtag instruction avr_reset and shift 1 in the reset register. 2. enter instruction prog_enable and shift 0b1010_0011_0111_0000 in the program- ming enable register. 26.9.14 leaving programming mode 1. enter jtag instruction prog_commands. 2. disable all programming instructions by using no operation instruction 11a. 3. enter instruction prog_enable and shift 0b0000_0000_0000_0000 in the program- ming enable register. 4. enter jtag instruction avr_reset and shift 0 in the reset register. tdi tdo d a t a flash eeprom fuses lock bits s trobe s addre ss s tate machine 314 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 26.9.15 performing chip erase 1. enter jtag instruction prog_commands. 2. start chip erase using programming instruction 1a. 3. poll for chip erase complete using prog ramming instruction 1b, or wait for t w lrh_ce (refer to table 26-13 on page 297 ). 26.9.16 programming the flash before programming the flash a chip erase must be performed, see ?performing chip erase? on page 314. 1. enter jtag instruction prog_commands. 2. enable flash write using programming instruction 2a. 3. load address high byte using programming instruction 2b. 4. load address low byte using programming instruction 2c. 5. load data using programming instructions 2d, 2e and 2f. 6. repeat steps 4 and 5 for all instruction words in the page. 7. w rite the page using programming instruction 2g. 8. poll for flash write complete using programming instruction 2h, or wait for t w lrh (refer to table 26-13 on page 297 ). 9. repeat steps 3 to 7 until all data have been programmed. a more efficient data transfer can be achieved using the prog_pageload instruction: 1. enter jtag instruction prog_commands. 2. enable flash write using programming instruction 2a. 3. load the page address using programming instructions 2b and 2c. pc w ord (refer to table 26-7 on page 286 ) is used to address within one page and must be written as 0. 4. enter jtag instruction prog_pageload. 5. load the entire page by shifting in all instruction words in the page byte-by-byte, starting with the lsb of the first instruction in the page and ending with the msb of the last instruction in the page. use update-dr to copy the contents of the flash data byte reg- ister into the flash page location and to auto-increment the program counter before each new word. 6. enter jtag instruction prog_commands. 7. w rite the page using programming instruction 2g. 8. poll for flash write complete using programming instruction 2h, or wait for t w lrh (refer to table 26-13 on page 297 ). 9. repeat steps 3 to 8 until all data have been programmed. 315 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 26.9.17 reading the flash 1. enter jtag instruction prog_commands. 2. enable flash read using programming instruction 3a. 3. load address using programming instructions 3b and 3c. 4. read data using programming instruction 3d. 5. repeat steps 3 and 4 until all data have been read. a more efficient data transfer can be ac hieved using the prog_pageread instruction: 1. enter jtag instruction prog_commands. 2. enable flash read using programming instruction 3a. 3. load the page address using programming instructions 3b and 3c. pc w ord (refer to table 26-7 on page 286 ) is used to address within one page and must be written as 0. 4. enter jtag instruction prog_pageread. 5. read the entire page (or flash) by shifting out all instruction words in the page (or flash), starting with the lsb of the first instruction in the page (flash) and ending with the msb of the last instruction in the page (flash). the capture-dr state both captures the data from the flash, and also auto-increments the program counter after each word is read. note that capture-dr comes before the shift-dr state. hence, the first byte which is shifted out contains valid data. 6. enter jtag instruction prog_commands. 7. repeat steps 3 to 6 until all data have been read. 26.9.18 programming the eeprom before programming the eeprom a chip erase must be per formed, see ?performing chip erase? on page 314. 1. enter jtag instruction prog_commands. 2. enable eeprom write using programming instruction 4a. 3. load address high byte using programming instruction 4b. 4. load address low byte using programming instruction 4c. 5. load data using programming instructions 4d and 4e. 6. repeat steps 4 and 5 for all data bytes in the page. 7. w rite the data using programming instruction 4f. 8. poll for eeprom write complete using programming instruction 4g, or wait for t w lrh (refer to table 26-13 on page 297 ). 9. repeat steps 3 to 8 until all data have been programmed. note that the prog_ pageload instruction can not be us ed when program ming the eeprom. 26.9.19 reading the eeprom 1. enter jtag instruction prog_commands. 2. enable eeprom read using programming instruction 5a. 3. load address using programming instructions 5b and 5c. 4. read data using programming instruction 5d. 5. repeat steps 3 and 4 until all data have been read. note that the prog_pageread instructio n can not be used when reading the eeprom. 316 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 26.9.20 programming the fuses 1. enter jtag instruction prog_commands. 2. enable fuse write using programming instruction 6a. 3. load data high byte using pr ogramming instructions 6b. a bit value of ?0? will program the corresponding fuse, a ?1? will unprogram the fuse. 4. w rite fuse high byte using programming instruction 6c. 5. poll for fuse write complete using programming instruction 6d, or wait for t w lrh (refer to table 26-13 on page 297 ). 6. load data low byte using pr ogramming instructions 6e. a ?0? will program the fuse, a ?1? will unprogram the fuse. 7. w rite fuse low byte using programming instruction 6f. 8. poll for fuse write complete using programming instruction 6g, or wait for t w lrh (refer to table 26-13 on page 297 ). 26.9.21 programming the lock bits 1. enter jtag instruction prog_commands. 2. enable lock bit write usin g programming instruction 7a. 3. load data using programming instructions 7b. a bit value of ?0? will program the corre- sponding lock bit, a ?1? will leave the lock bit unchanged. 4. w rite lock bits using programming instruction 7c. 5. poll for lock bit write complete using pr ogramming instruction 7d, or wait for t w lrh (refer to table 26-13 on page 297 ). 26.9.22 reading the fuses and lock bits 1. enter jtag instruction prog_commands. 2. enable fuse/lock bit read using programming instruction 8a. 3. to read all fuses and lock bits, use programming instruction 8e. to only read fuse high byte, use programming instruction 8b. to only read fuse low byte, use programming instruction 8c. to only read lock bits, use programming instruction 8d. 26.9.23 reading the signature bytes 1. enter jtag instruction prog_commands. 2. enable signature byte read using programming instruction 9a. 3. load address 0x00 using programming instruction 9b. 4. read first signature byte us ing programming instruction 9c. 5. repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third signature bytes, respectively. 26.9.24 reading the calibration byte 1. enter jtag instruction prog_commands. 2. enable calibration byte read using programming instruction 10a. 3. load address 0x00 using programming instruction 10b. 4. read the calibration byte using programming instruction 10c. 317 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 27. electrical characteristics 27.1 absolute maximum ratings* 27.2 dc characteristics operating temperature.................................. -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c voltage on any pin except reset with respect to ground ................................-0.5v to v cc +0.5v voltage on reset with respect to ground......-0.5v to +13.0v maximum operating voltage ............................................ 6.0v dc current per i/o pin.................................................40.0 ma dc current v cc and gnd pins................................ 200.0 ma t a = -40 c to 85 c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units v il input low voltage except xtal1 and reset pins v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v -0.5 -0.5 0.2v cc (1) 0.3v cc (1) v v il1 input low voltage xtal1 pins v cc = 1.8v - 5.5v -0.5 0.1v cc (1) v v il2 input low voltage, reset pins v cc = 1.8v - 5.5v -0.5 0.1v cc (1) v v ih input high voltage except xtal1 and reset pins v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v 0.7v cc (2) 0.6v cc (2) v cc + 0.5 v cc + 0.5 v v ih1 input high voltage, xtal1 pin v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v 0.8v cc (2) 0.7v cc (2) v cc + 0.5 v cc + 0.5 v v ih2 input high voltage, reset pins v cc = 1.8v - 5.5v 0.85v cc (2) v cc + 0.5 v v ol output low voltage (3) , port a, c, d, e, f, g i ol = 10 ma, v cc = 5v i ol = 5 ma, v cc = 3v 0.9 0.6 v v ol1 output low voltage (3) , port b i ol = 20 ma, v cc = 5v i ol = 10 ma, v cc = 3v 0.7 0.5 v v oh output high voltage (4) , port a, c, d, e, f, g i oh = -10 ma, v cc = 5v i oh = -5 ma, v cc = 3v 4.2 2.3 v v oh1 output high voltage (4) , port b i oh = -20 ma, v cc = 5v i oh = -10 ma, v cc = 3v 4.2 2.3 v i il input leakage current i/o pin v cc = 5.5v, pin low (absolute value) 1a i ih input leakage current i/o pin v cc = 5.5v, pin high (absolute value) 1a r rst reset pull-up resistor 20 100 k r pu i/o pin pull-up resistor 20 100 k 318 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 note: 1. ?max? means the highest value where the pin is guaranteed to be read as low 2. ?min? means the lowest value where t he pin is guaranteed to be read as high 3. although each i/o port can sink more than the test conditions (20 ma at v cc = 5v, 10 ma at v cc = 3v for port b and 10 ma at v cc = 5v, 5 ma at v cc = 3v for all other ports) under steady state conditions (non-transient), the following must be observed: tqfp and qfn/mlf package: 1] the sum of all iol, for all ports, should not exceed 400 ma. 2] the sum of all iol, for ports a0 - a7, c4 - c7, g2 should not exceed 100 ma. 3] the sum of all iol, for ports b0 - b7, e0 - e7, g3 - g5 should not exceed 100 ma. 4] the sum of all iol, for ports d0 - d7, c0 - c3, g0 - g1 should not exceed 100 ma. 5] the sum of all iol, for ports f0 - f7, should not exceed 100 ma. if iol exceeds the test condition, vol may exceed the related sp ecification. pins are not guar anteed to sink current greater than the listed test condition. 4. although each i/o port can source more than the test conditions (20 ma at v cc = 5v, 10 ma at v cc = 3v for port b and 10ma at v cc = 5v, 5 ma at v cc = 3v for all other ports) under steady state conditions (non-transient), the following must be observed: tqfp and qfn/mlf package: 1] the sum of all ioh, for a ll ports, should not exceed 400 ma. 2] the sum of all ioh, for ports a0 - a7 , c4 - c7, g2 should not exceed 100 ma. 3] the sum of all ioh, for ports b0 - b7, e0 - e7, g3 - g5 should not exceed 100 ma. 4] the sum of all ioh, for ports d0 - d7, c0 - c3, g0 - g1 should not exceed 100 ma. 5] the sum of all ioh, for ports f0 - f7, should not exceed 100 ma. if ioh exceeds the test condition, voh ma y exceed the related specification. pins are not guaranteed to source current greater than the listed test condition. v acio analog comparator input offset voltage v cc = 5v v in = v cc /2 <10 40 mv i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 -50 50 na t acpd analog comparator propagation delay v cc = 2.7v v cc = 4.0v 750 500 ns t a = -40 c to 85 c, v cc = 1.8v to 5.5v (unless otherwise noted) (continued) symbol parameter condition min. typ. max. units 319 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 27.2.1 atmega165a dc characteristics notes: 1. all bits set in the ?power reduction register? on page 34 2. typical values at 25 c. maximum values are characterized values and not test limits in production 27.2.2 atmega165pa dc characteristics notes: 1. all bits set in the ?power reduction register? on page 34 2. typical values at 25 c. maximum values are characterized values and not test limits in production table 27-1. t a = -40 c to 85 c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.35 0.44 ma active 4mhz, v cc = 3v 2.3 2.5 ma active 8mhz, v cc = 5v 8.4 9.5 ma idle 1mhz, v cc = 2v 0.1 0.2 ma idle 4mhz, v cc = 3v 0,7 0.8 ma idle 8mhz, v cc = 5v 3.0 3.3 ma power-save mode (2) 32khz tosc enabled, v cc = 1.8v 0.55 1.6 a 32khz tosc enabled, v cc = 3v 0.8 2.6 a power-down mode (2) w dt enabled, v cc = 3v 6 10 a w dt disabled, v cc = 3v 0.2 2 a table 27-2. t a = -40 c to 85 c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.35 0.44 ma active 4mhz, v cc = 3v 2.3 2.5 ma active 8mhz, v cc = 5v 8.4 9.5 ma idle 1mhz, v cc = 2v 0.1 0.2 ma idle 4mhz, v cc = 3v 0,7 0.8 ma idle 8mhz, v cc = 5v 3.0 3.3 ma power-save mode (2) 32khz tosc enabled, v cc = 1.8v 0.55 1.6 a 32khz tosc enabled, v cc = 3v 0.8 2.6 a power-down mode (2) w dt enabled, v cc = 3v 6 10 a w dt disabled, v cc = 3v 0.2 2 a 320 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 27.2.3 atmega325a dc characteristics tbd notes: 1. all bits set in the ?power reduction register? on page 41 . 2. typical values at 25 c. maximum values are characterized values and not test limits in production. 27.2.4 atmega325pa dc characteristics tbd notes: 1. all bits set in the ?power reduction register? on page 41 . 2. typical values at 25 c. maximum values are characterized values and not test limits in production. table 27-3. t a = -40 c to 85 c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units i cc power supply current (1) active 1mhz, v cc = 2v ma active 4mhz, v cc = 3v ma active 8mhz, v cc = 5v ma idle 1mhz, v cc = 2v ma idle 4mhz, v cc = 3v ma idle 8mhz, v cc = 5v ma power-save mode (2) 32khz tosc enabled, v cc = 1.8v a 32khz tosc enabled, v cc = 3v a power-down mode (2) w dt enabled, v cc = 3v a w dt disabled, v cc = 3v a table 27-4. t a = -40 c to 85 c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units i cc power supply current (1) active 1mhz, v cc = 2v ma active 4mhz, v cc = 3v ma active 8mhz, v cc = 5v ma idle 1mhz, v cc = 2v ma idle 4mhz, v cc = 3v ma idle 8mhz, v cc = 5v ma power-save mode (2) 32khz tosc enabled, v cc = 1.8v a 32khz tosc enabled, v cc = 3v a power-down mode (2) w dt enabled, v cc = 3v a w dt disabled, v cc = 3v a 321 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 27.2.5 atmega3250a dc characteristics tbd notes: 1. all bits set in the ?power reduction register? on page 41 . 2. typical values at 25 c. maximum values are characterized values and not test limits in production. 27.2.6 atmega3250pa dc characteristics tbd notes: 1. all bits set in the ?power reduction register? on page 41 . 2. typical values at 25 c. maximum values are characterized values and not test limits in production. table 27-5. t a = -40 c to 85 c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units i cc power supply current (1) active 1mhz, v cc = 2v ma active 4mhz, v cc = 3v ma active 8mhz, v cc = 5v ma idle 1mhz, v cc = 2v ma idle 4mhz, v cc = 3v ma idle 8mhz, v cc = 5v ma power-save mode (2) 32khz tosc enabled, v cc = 1.8v a 32khz tosc enabled, v cc = 3v a power-down mode (2) w dt enabled, v cc = 3v a w dt disabled, v cc = 3v a table 27-6. t a = -40 c to 85 c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units i cc power supply current (1) active 1mhz, v cc = 2v ma active 4mhz, v cc = 3v ma active 8mhz, v cc = 5v ma idle 1mhz, v cc = 2v ma idle 4mhz, v cc = 3v ma idle 8mhz, v cc = 5v ma power-save mode (2) 32khz tosc enabled, v cc = 1.8v a 32khz tosc enabled, v cc = 3v a power-down mode (2) w dt enabled, v cc = 3v a w dt disabled, v cc = 3v a 322 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 27.2.7 atmega645a dc characteristics notes: 1. all bits set in the ?power reduction register? on page 41 . 2. typical values at 25 c. maximum values are characterized values and not test limits in production. 27.2.8 atmega645p dc characteristics notes: 1. all bits set in the ?power reduction register? on page 41 . 2. typical values at 25 c. maximum values are characterized values and not test limits in production. table 27-7. t a = -40 c to 85 c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units i cc power supply current (1) active 1mhz, v cc = 2v 1.5 ma active 4mhz, v cc = 3v 3.5 active 8mhz, v cc = 5v 12 idle 1mhz, v cc = 2v 0.45 idle 4mhz, v cc = 3v 1.5 idle 8mhz, v cc = 5v 5.5 power-save mode (2) 32khz tosc enabled, v cc = 1.8v a 32khz tosc enabled, v cc = 3v power-down mode (2) w dt enabled, v cc = 3v 7 15 w dt disabled, v cc = 3v 0.25 2 table 27-8. t a = -40 c to 85 c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units i cc power supply current (1) active 1mhz, v cc = 2v 1.04 1.15 ma active 4mhz, v cc = 3v 1.7 1.8 active 8mhz, v cc = 5v 5.8 6.2 idle 1mhz, v cc = 2v 0.25 0.28 idle 4mhz, v cc = 3v 0.39 0.43 idle 8mhz, v cc = 5v 1.6 1.7 power-save mode (2) 32khz tosc enabled, v cc = 1.8v 0.75 2.7 a 32khz tosc enabled, v cc = 3v 0.8 2.8 power-down mode (2) w dt enabled, v cc = 3v 7 10 w dt disabled, v cc = 3v 0.25 2 323 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 27.2.9 atmega6450a dc characteristics notes: 1. all bits set in the ?power reduction register? on page 41 . 2. typical values at 25 c. maximum values are characterized values and not test limits in production. 27.2.10 atmega6450p dc characteristics notes: 1. all bits set in the ?power reduction register? on page 41 . 2. typical values at 25 c. maximum values are characterized values and not test limits in production. table 27-9. t a = -40 c to 85 c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units i cc power supply current (1) active 1mhz, v cc = 2v 1.5 ma active 4mhz, v cc = 3v 3.5 active 8mhz, v cc = 5v 12 idle 1mhz, v cc = 2v 0.45 idle 4mhz, v cc = 3v 1.5 idle 8mhz, v cc = 5v 5.5 power-save mode (2) 32khz tosc enabled, v cc = 1.8v a 32khz tosc enabled, v cc = 3v power-down mode (2) w dt enabled, v cc = 3v 7 15 w dt disabled, v cc = 3v 0.25 2 table 27-10. t a = -40 c to 85 c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units i cc power supply current (1) active 1mhz, v cc = 2v 1.04 1.15 ma active 4mhz, v cc = 3v 1.7 1.8 active 8mhz, v cc = 5v 5.8 6.2 idle 1mhz, v cc = 2v 0.25 0.28 idle 4mhz, v cc = 3v 0.39 0.43 idle 8mhz, v cc = 5v 1.6 1.7 power-save mode (2) 32khz tosc enabled, v cc = 1.8v 0.75 2.7 a 32khz tosc enabled, v cc = 3v 0.8 2.8 power-down mode (2) w dt enabled, v cc = 3v 7 10 w dt disabled, v cc = 3v 0.25 2 324 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 27.3 speed grades maximum frequency is depending on v cc. as shown in figure 27-1 on page 324 , the maximum frequency vs. v cc curve is linear between 1.8v < v cc < 2.7v and between 2.7v < v cc < 4.5v. figure 27-1. maximum frequency vs. v cc , atmega165a/165pa/atmega645a/atmega645p figure 27-2. maximum frequency vs. v cc (10 - 20mhz) atmega325a/atmega325pa/atmega3250a/atmega3250pa/atmega6450a/ atmega6450p 4 mhz 1. 8v 2.7 v 4.5 v 8 mhz 16 mhz 5.5 v safe operating area 4 mhz 1. 8v 2.7 v 4.5 v 10 mhz 20 mhz 5.5 v safe operating area 325 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 27.4 clock characteristics 27.4.1 calibrated internal rc oscillator accuracy notes: 1. voltage range for atmega165a/165pa/325a/ 325pa/3250a/3250pa/645a/645p/6450a/6450p. 27.4.2 external clock drive waveforms figure 27-3. external clock drive w aveforms 27.4.3 external clock drive table 27-11. calibration accuracy of internal rc oscillator frequency v cc temperature calibration accuracy factory calibration 8.0mhz 3v 25 c10% user calibration 7.3 - 8.1mhz 1.8v - 5.5v (1) -40 c - 85 c1% v il1 v ih1 table 27-12. external clock drive symbol parameter v cc =1.8-5.5v v cc =2.7-5.5v v cc =4.5-5.5v units min. max. min. max. min. max. 1/t clcl oscillator frequency 04010020mhz t clcl clock period 1000 100 50 ns t chcx high time 400 40 20 ns t clcx low time 400 40 20 ns t clch rise time 2.0 1.6 0.5 s t chcl fall time 2.0 1.6 0.5 s t clcl change in period from one clock cycle to the next 22 2% 326 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 27.5 system and reset characteristics the following characteristics apply only to atmega165a/165pa note: 1. the power-on reset will not work unless the supply voltage has been below v pot (falling) 27.6 power-on reset 27.6.1 atmega169a/169pa/329a/329pa/3290a/3290pa/649a/649p/6490a/6490pa revision c and later notes: 1. the power-on reset will not work un less the supply voltage has been below v pot (falling) table 27-13. reset, brown-out and internal voltage characteristics symbol parameter condition min typ max units v pot power-on reset threshold voltage (rising) t a = -40c to 85c 1.1 1.4 1.6 v power-on reset threshold voltage (falling) (1) t a = -40c to 85c 0.6 1.3 1.6 v v psr power-on reset slope rate 0.1 4.5 v/ms v rst reset pin threshold voltage v cc = 3v 0.2 v cc 0.9 v cc v t rst minimum pulse width on reset pin v cc = 3v 2.5 s v hyst brown-out detector hysteresis 50 mv t bod min pulse w idth on brown-out reset 2s v bg bandgap reference voltage v cc = 2.7v, t a =25c 1.0 1.1 1.2 v t bg bandgap reference start-up time v cc = 2.7v, t a =25c 40 70 s i bg bandgap reference current consumption v cc = 2.7v, t a =25c 10 a table 27-14. reset, brown-out and internal voltage reference characteristics, t a = -40c to 85c symbol parameter min. typ max units v pot power-on reset threshold voltage (rising) 1.1 1.4 1.6 v power-on reset threshold voltage (falling) (1) 0.6 1.3 1.6 v sr on power-on slope rate 0.01 10 v/ms 327 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 27.6.2 atmega325a/325pa/3250a/3250pa/645a/645p/6450a/6450pa revision a and b note: 1. the power-on reset will not work unless the supply voltage has been below v pot (falling) 27.7 brown-out detection note: 1. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, the device is tested down to v cc = v bot during the production test. this guar- antees that a brown-out reset will occur before v cc drops to a voltage where correct operation of the microcontroller is no long er guaranteed. the test is performed using bodlevel = 110, 101, and 100. 27.8 external interrup ts characteristics table 27-15. reset, brown-out, and internal voltage reference characteristics, t a = -40c to 85c symbol parameter min. typ max units v pot power-on reset threshold voltage (rising) 0.7 1.0 1.4 v power-on reset threshold voltage (falling) (1) 0.05 0.9 1.3 sr on power-on slope rate 0.01 4.5 v/ms table 27-16. bodlevel fuse coding (1) bodlevel 2...0 fuses min v bot typ v bot max v bot units 111 bod disabled 110 1.7 1.8 2.0 v 101 2.5 2.7 2.9 100 4.1 4.3 4.5 011 reserved 010 001 000 table 27-17. asynchronous external interrupt characteristics symbol parameter condition min typ max units t int minimum pulse width for asynchronous external interrupt 50 ns 328 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 27.9 spi timing characteristics see figure 27-4 on page 328 and figure 27-5 on page 329 for details. note: 1. in spi programming mode the minimum sck high/low period is: - 2 t clcl for f ck < 12mhz - 3 t clcl for f ck > 12mhz figure 27-4. spi interface timing requirements (master mode) table 27-18. spi timing parameters description mode min typ max 1 sck period master see table 18-5 ns 2 sck high/low master 50% duty cycle 3 rise/fall time master 3.6 4 setup master 10 5hold master 10 6 out to sck master 0.5 ? t sck 7 sck to out master 10 8 sck to out high master 10 9ss low to out slave 15 10 sck period slave 4 ? t ck 11 sck high/low (1) slave 2 ? t ck 12 rise/fall time slave 1.6 s 13 setup slave 10 ns 14 hold slave t ck 15 sck to out slave 15 16 sck to ss high slave 20 17 ss high to tri-state slave 10 18 ss low to sck slave 20 ? t ck mo s i (data output) s ck (cpol = 1) mi s o (data input) s ck (cpol = 0) ss m s bl s b l s b m s b ... ... 61 22 3 45 8 7 329 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 27-5. spi interface timing requirements (slave mode) mi so (data output) s ck (cpol = 1) mo si (data input) s ck (cpol = 0) ss m s bl s b l s b m s b ... ... 10 11 11 12 1 3 14 17 15 9 x 16 330 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 28. adc characteristics table 28-1. adc characteristics symbol parameter condition min typ max units resolution single ended conversion 10 bits differential conversion 8 bits absolute accuracy (including inl, dnl, quantization error, gain and offset error) single ended conversion v ref = 4v, v cc = 4v, adc clock = 200khz 22.5lsb single ended conversion v ref = 4v, v cc = 4v, adc clock = 1mhz 2.5 lsb single ended conversion v ref = 4v, v cc = 4v, adc clock = 200khz noise reduction mode 2lsb single ended conversion v ref = 4v, v cc = 4v, adc clock = 1mhz noise reduction mode 2.5 lsb integral non-linearity (inl) single ended conversion v ref = 4v, v cc = 4v, adc clock = 200khz 1.25 lsb differential non-linearity (dnl) single ended conversion v ref = 4v, v cc = 4v, adc clock = 200khz 0.25 lsb gain error single ended conversion v ref = 4v, v cc = 4v, adc clock = 200khz 2lsb offset error single ended conversion v ref = 4v, v cc = 4v, adc clock = 200khz 1.25 lsb conversion time free running conversion 13 260 s clock frequency single ended conversion 50 1000 khz avcc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage single ended conversion 1.0 avcc v differential conversion 1.0 avcc - 0.5 v v in pin input voltage single ended channels gnd v ref v differential channels gnd avcc v input range single ended channels gnd v ref v differential channels (1) -0.85v ref v ref v input bandwidth single ended channels 38.5 khz differential channels 4 khz 331 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 note: 1. voltage difference between channels. v int internal voltage reference 1.0 1.1 1.2 v r ref reference input resistance 32 k r ain analog input resistance 100 m table 28-1. adc characteristics (continued) symbol parameter condition min typ max units 332 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29. typical characteristics the following charts show typical behavior. t hese figures are not tested during manufacturing. all current consumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups enabled. a sine wave generator with rail-to-rail output is used as clock source. all active- and idle current consumption measurements are done with all bits in the prr register set and thus, the corresponding i/o modules are turned off. also the analog comparator is dis- abled during these measurements. table 29-1 on page 337 and table 29-2 on page 337 show the additional current consumption compared to i cc active and i cc idle for every i/o module con- trolled by the power reduction register. see ?power reduction register? on page 41 for details. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient tempera- ture. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l * v cc *f where c l = load capacitance, v cc = operating voltage and f = average switching frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with w atchdog timer enabled and power-down mode with w atchdog timer disabled represents the differential cur- rent drawn by the w atchdog timer. 29.1 atmega165a 29.1.1 active supply current figure 29-1. atmega165a: active supply current vs. frequency (0.1 - 1.0mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.05 0.1 0.15 0.2 0.25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 333 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-2. atmega165a: active supply current vs. frequency (1 - 16mhz) figure 29-3. atmega165a: active supply current vs. v cc (internal rc oscillator, 8mhz 0 1 2 3 4 5 6 7 8 9 10 11 0246 8 10 12 14 16 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 8 5 c 25 c -45 c 0 1 2 3 4 5 6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 334 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-4. atmega165a: active supply current vs. v cc (internal rc oscillator, 1mhz) figure 29-5. atmega165a: active supply current vs. v cc (32khz w atch crystal) 8 5 c 25 c -45 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.522.533.544.555.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 0 5 10 15 20 25 30 35 40 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( a) 335 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.1.2 idle supply current figure 29-6. atmega165a: idle supply current vs. frequency (0.1 - 1.0mhz) figure 29-7. atmega165a: idle supply current vs. frequency (1 - 16mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.05 0.1 0.15 0.2 0.25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 0 0.5 1 1.5 2 2.5 3 3.5 0246 8 10 12 14 16 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 336 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-8. atmega165a: idle supply current vs. v cc (internal rc o scillator, 8mhz) figure 29-9. atmega165a: idle supply current vs. v cc (internal rc o scillator, 1 mhz) 8 5 c 25 c -45 c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.522.533.544.555.5 v cc ( v ) i cc (ma) 337 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-10. atmega165a: idle supply current vs. v cc (32khz w atch crystal) 29.1.3 atmega165a: supply current of i/o modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules are controlled by the power reduction register. see ?power reduction register? on page 41 for details. 8 5 c 25 c -45 c 0 1 2 3 4 5 6 7 8 9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( a) table 29-1. atmega165a additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz pradc 7 a 44 a 195 a prusart0 6.9 a 43.5 a 210 a prspi 6.6 a 47 a 205 a prtim1 7 a 47 a 206 a table 29-2. atmega165a: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 29-1 and figure 29-2 ) additional current consumption compared to idle with external clock (see figure 29-6 and figure 29-7 ) pradc 3.2% 12.7% prusart0 3.4% 13.1% prspi 3.3% 13.0% prtim1 3.4% 13.2% 338 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 it is possible to calculate the typical current consumption based on the numbers from table 29-2 for other v cc and frequency settings than listed in table 29-1 . 29.1.3.1 example 1 calculate the expected current consumption in idle mode with usart0, timer1, and spi enabled at v cc = 3.0v and f = 1mhz. from table 29-2 , second column, we see that we need to add 13.1% for the usart0, 13.0% for the spi, and 13.2% for the timer1 module. reading from figure 29-6 , we find that the idle current consumption is ~0.09 ma at v cc = 3.0v and f = 1mhz. the total current consumption in id le mode with usart0, timer1, and spi enabled, gives: 29.1.4 power-down supply current figure 29-11. atmega165a: power-down supply current vs. v cc ( w atchdog timer disabled) i cc total 0.09 ma 1 0.131 0.13 0.132 +++ () ? 0.13 ma ? 8 5 c 25 c -45 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 339 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-12. atmega165a: power-down supply current vs. v cc ( w atchdog timer enabled) 29.1.5 power-save supply current figure 29-13. atmega165a: power-save supply current vs. v cc ( w atchdog timer disabled) the differential current consumption between power-save with w d disabled and 32khz tosc represents the current drawn by timer/counter2. 8 5 c 25 c -45 c 0 2 4 6 8 10 12 14 16 1 8 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 1.522.533.544.555.5 v cc ( v ) i cc ( a) 340 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.1.6 standby supply current figure 29-14. atmega165a: standby supply current vs. v cc (32khz w atch crystal, w atchdog timer disabled) figure 29-15. atmega165a: standby supply current vs. v cc (xtall and resonator, w atchdog timer disabled) 8 5 c 25 c -45 c 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 1.522.533.544.555.5 v cc ( v ) i cc ( a) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 1mhz_res 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0.1 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 341 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.1.7 pin pull-up figure 29-16. atmega165a: i/o pin pull-up resistor current vs. input voltage (v cc = 5v) figure 29-17. atmega165a: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) 8 5 c 25 c 0 25 50 75 100 125 150 00.511.522.533.544.55 v op ( v ) i op ( u a) -45 c 8 5 c 0 10 20 30 40 50 60 70 8 0 0 0.5 1 1.5 2 2.5 3 v op ( v ) i op ( u a) 25 c -45 c 342 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-18. atmega165a: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8v) figure 29-19. atmega165a: reset pull-up resistor current vs. reset pin voltage (v cc = 5v) 8 5 c 25 c 0 5 10 15 20 25 30 35 40 45 50 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v op ( v ) i op ( u a) -45 c 8 5 c 25 c -45 c 0 20 40 60 8 0 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset ( v ) i reset ( u a) 343 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-20. atmega165a: reset pull-up resistor current vs. reset pin voltage (v cc = 2.7v) figure 29-21. atmega165a: reset pull-up resistor current vs. reset pin voltage (v cc = 1.8v) 8 5 c 25 c -45 c 0 10 20 30 40 50 60 0 0.5 1 1.5 2 2.5 3 v reset ( v ) i reset ( u a) 8 5 c 25 c -45 c 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v reset ( v ) i reset ( u a) 344 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.1.8 pin driver strength figure 29-22. atmega165a: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =5v) figure 29-23. atmega165a: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =2.7v) 8 5 c 25 c -45 c 4.55 4.6 4.65 4.7 4.75 4. 8 4. 8 5 4.9 4.95 5 5.05 01234567 8 910 i oh (ma) v oh ( v ) 85 c 25 c -45 c 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 0246810 i oh (ma) v oh (v) 345 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-24. atmega165a: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =1.8v) figure 29-25. atmega165a: i/o pin output voltage vs. source current, port b (v cc = 5v) 8 5 c 25 c -45 c 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1. 8 1.9 0 0.5 1 1.5 2 2.5 3 3.5 4 i oh (ma) v oh ( v ) 8 5 c 25 c -45 c 4.3 4.4 4.5 4.6 4.7 4. 8 4.9 5 5.1 0246 8 10 12 14 16 1 8 20 i oh (ma) v oh ( v ) 346 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-26. atmega165a: i/o pin output voltage vs. source current, port b (v cc = 2.7v) figure 29-27. atmega165a: i/o pin output voltage vs. source current, port b (v cc = 1.8v) 8 5 c 25 c -45 c 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 2.6 2. 8 0246 8 10 12 14 16 1 8 20 i oh (ma) v oh ( v ) 85 c 25 c -45 c 1.3 1.4 1.5 1.6 1.7 1.8 1.9 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i oh (ma) v oh (v) 347 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-28. atmega165a: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 5v) figure 29-29. atmega165a: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 2.7v) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 01234567 8 910 i ol (ma) v ol ( v ) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 1.1 01234567 8 910 i ol (ma) v ol ( v ) 348 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-30. atmega165a: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 1.8v) figure 29-31. atmega165a: i/o pin output voltage vs. sink current, port b (v cc = 5v) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 3 i ol (ma) v ol ( v ) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol ( v ) 349 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-32. atmega165a: i/o pin output voltage vs. sink current, port b (v cc = 2.7v) figure 29-33. atmega165a: i/o pin output voltage vs. sink current, port b (v cc = 1.8v) 8 5 c 25 c -45 c 0 0.2 0.4 0.6 0. 8 1 1.2 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol ( v ) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0123456 i ol (ma) v ol ( v ) 350 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.1.9 pin thresholds and hysteresis figure 29-34. atmega165a: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 29-35. atmega165a: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0?) 85 c 25 c -45 c 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) thre s hold (v) 8 5 c 25 c -45 c 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 351 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-36. atmega165a: i/o pin input hysteresis vs. v cc figure 29-37. atmega165a: reset input threshold voltage vs. v cc (v ih ,reset pin read as ?1?) 85 c 25 c -45 c 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (mv) 8 5 c 25 c -45 c 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 352 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-38. atmega165a: reset input threshold voltage vs. v cc (v il ,reset pin read as ?0?) figure 29-39. atmega165a: reset input pin hysteresis vs. v cc 8 5 c 25 c -45 c 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 85 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) 353 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.1.10 bod thresholds and analog comparator offset figure 29-40. atmega165a: bod thresholds vs. temperature (bod level is 4.3v) figure 29-41. atmega165a: bod thresholds vs. temperature (bod level is 2.7v) rising v cc falling v cc 4.23 4.25 4.27 4.29 4.31 4.33 4.35 4.37 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) rising v cc falling v cc 2.662 2.677 2.692 2.707 2.722 2.737 2.752 2.767 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) 354 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-42. atmega165a: bod thresholds vs. temperature (bod level is 1.8v) figure 29-43. atmega165a: bandgap voltage vs. v cc rising v cc falling v cc 1.7 8 6 1.791 1.796 1. 8 01 1. 8 06 1. 8 11 1. 8 16 1. 8 21 1. 8 26 1. 8 31 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) 8 5 c 25 c -45 c 1.065 1.07 1.075 1.0 8 1.0 8 5 1.09 1.095 1.1 1.105 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) bandgap v oltage ( v ) 355 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-44. atmega165a: bandgap voltage vs. temperature figure 29-45. atmega165a: analog comparator offset voltage vs. common mode voltage (v cc = 5v) 5.5 v 4.0 v 2.7 v 1. 8 v 1.067 1.072 1.077 1.0 8 2 1.0 8 7 1.092 1.097 1.102 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bandgap v oltage ( v ) 8 5 c 25 c -40 c 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 common mode v oltage ( v ) comparator offset v oltage ( v ) 356 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-46. atmega165a: analog comparator offset voltage vs. common mode voltage (v cc =2.7v) 29.1.11 internal oscillator speed figure 29-47. atmega165a: w atchdog oscillator frequency vs. v cc 8 5 c 25 c -40 c 0 0.0005 0.001 0.0015 0.002 0.0025 0.003 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 common mode v oltage ( v ) comparator offset v oltage ( v ) 8 5 c 25 c -45 c 1000 1050 1100 1150 1200 1250 1300 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) f rc (khz) 357 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-48. atmega165a: w atchdog oscillator freq uency vs. temperature figure 29-49. atmega165a: calibrated 8mhz rc osc illator frequency vs. temperature 5.5 v 5.0 v 4.5 v 4.0 v 3.0 v 2.7 v 1. 8 v 1000 1050 1100 1150 1200 1250 1300 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re (c) f rc (khz) 5.5 v 4.5 v 3.3 v 1. 8 v 7.5 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 -50 -30 -10 10 30 50 70 90 temperat u re (c) f rc (mhz) 358 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-50. atmega165a: calibrated 8mhz rc oscillator frequency vs. v cc figure 29-51. atmega165a: calibrated 8mhz rc osc illator frequency vs . osccal value 8 5 c 25 c -45 c 7.5 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) f rc (mhz) 8 5 c -45 c 0 2 4 6 8 10 12 14 16 016324 8 64 8 0 96 112 12 8 144 160 176 192 20 8 224 240 256 osccal (x1) f rc (mhz) 25 c 359 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.1.12 current consumption of peripheral units figure 29-52. atmega165a: brownout detector current vs. v cc figure 29-53. atmega165a: active supply current with adc at 50khz vs. v cc 8 5 c 25 c -45 c 12 16 20 24 2 8 32 36 40 44 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 85 c 25 c -45 c 150 175 200 225 250 275 300 325 350 375 400 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc ( u a) 360 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-54. atmega165a: active supply current with adc at 200khz vs. v cc figure 29-55. atmega165a: active supply current with adc at 1mhz vs. v cc 85 c 25 c -45 c 150 175 200 225 250 275 300 325 350 375 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc ( u a) 85 c 25 c -45 c 125 150 175 200 225 250 275 300 325 350 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc ( u a) 361 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-56. atmega165a: aref external reference current vs. v cc figure 29-57. atmega165a: w atchdog timer current vs. v cc 85 c 25 c -45 c 40 60 80 100 120 140 160 180 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc ( u a) 8 5 c 25 c -45 c 0 5 10 15 20 25 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 362 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-58. atmega165a: analog comparator current vs. v cc figure 29-59. atmega165a: programming current vs. v cc 85 c 25 c -45 c 30 35 40 45 50 55 60 65 70 75 80 85 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc ( u a) 8 5 c 25 c -45 c 0 2 4 6 8 10 12 14 16 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 363 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.1.13 current consumption in reset and reset pulsewidth figure 29-60. atmega165a: reset supply current vs. v cc (0.1 - 1.0mhz, excluding current through the reset pull-up) figure 29-61. atmega165a: reset supply current vs. v cc (1 - 16mhz, excluding current through the reset pull-up) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 0246 8 10 12 14 16 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 364 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-62. atmega165a: minimum reset pulse w idth vs. v cc 8 5 c 25 c -45 c 0 400 8 00 1200 1600 2000 2400 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) p u lse w idth (ns) 365 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.2 atmega165pa 29.2.1 active supply current figure 29-63. atmega165pa: active supply current vs. frequency (0.1 - 1.0mhz) figure 29-64. atmega165pa: active supply current vs. frequency (1 - 16mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.05 0.1 0.15 0.2 0.25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 0 1 2 3 4 5 6 7 8 9 10 11 0246 8 10 12 14 16 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 366 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-65. atmega165pa: active supply current vs. v cc (internal rc oscillator, 8mhz figure 29-66. atmega165pa: active supply current vs. v cc (internal rc oscillator, 1mhz) 8 5 c 25 c -45 c 0 1 2 3 4 5 6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.522.533.544.555.5 v cc ( v ) i cc (ma) 367 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-67. atmega165pa: active supply current vs. v cc (32khz w atch crystal) 29.2.2 idle supply current figure 29-68. atmega165pa: idle supply current vs. frequency (0.1 - 1.0mhz) 8 5 c 25 c -45 c 0 5 10 15 20 25 30 35 40 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( a) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.05 0.1 0.15 0.2 0.25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 368 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-69. atmega165pa: idle supply current vs. frequency (1 - 16mhz) figure 29-70. atmega165pa: idle supply current vs. v cc (internal rc oscillator, 8mhz) 0 0.5 1 1.5 2 2.5 3 3.5 0246 8 10 12 14 16 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 8 5 c 25 c -45 c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 369 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-71. atmega165pa: idle supply current vs. v cc (internal rc oscillator, 1 mhz) figure 29-72. atmega165a: idle supply current vs. v cc (32khz w atch crystal) 29.2.3 atmega165a: supply current of i/o modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules 8 5 c 25 c -45 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.522.533.544.555.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 0 1 2 3 4 5 6 7 8 9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( a) 370 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 are controlled by the power reduction register. see ?power reduction register? on page 41 for details. it is possible to calculate the typical current consumption based on the numbers from table 29-2 for other v cc and frequency settings than listed in table 29-1 . 29.2.3.1 example 1 calculate the expected current consumption in idle mode with usart0, timer1, and spi enabled at v cc = 3.0v and f = 1mhz. from table 29-2 , second column, we see that we need to add 13.1% for the usart0, 13.0% for the spi, and 13.2% for the timer1 module. reading from figure 29-6 , we find that the idle current consumption is ~0.09 ma at v cc = 3.0v and f = 1mhz. the total current consumption in idle mode with usart0, timer1, and spi enabled, gives: table 29-3. atmega165pa: additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz pradc 7 a 44 a 195 a prusart0 6.9 a 43.5 a 210 a prspi 6.6 a 47 a 205 a prtim1 7 a 47 a 206 a table 29-4. atmega165pa: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 29-1 and figure 29-2 ) additional current consumption compared to idle with external clock (see figure 29-6 and figure 29-7 ) pradc 3.2% 12.7% prusart0 3.4% 13.1% prspi 3.3% 13.0% prtim1 3.4% 13.2% i cc total 0.09 ma 1 0.131 0.13 0.132 +++ () ? 0.13 ma ? 371 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.2.4 power-down supply current figure 29-73. atmega165pa: power-down supply current vs. v cc ( w atchdog timer disabled) figure 29-74. atmega165pa: power-down supply current vs. v cc ( w atchdog timer enabled) 8 5 c 25 c -45 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 0 2 4 6 8 10 12 14 16 1 8 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 372 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.2.5 power-save supply current figure 29-75. atmega165pa: power-save supply current vs. v cc ( w atchdog timer disabled) the differential current consumption between power-save with w d disabled and 32khz tosc represents the current drawn by timer/counter2. 29.2.6 standby supply current figure 29-76. atmega165pa: standby supply current vs. v cc (32khz w atch crystal, w atch- dog timer disabled) 8 5 c 25 c -45 c 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 1.522.533.544.555.5 v cc ( v ) i cc ( a) 8 5 c 25 c -45 c 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 1.522.533.544.555.5 v cc ( v ) i cc ( a) 373 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-77. atmega165pa: standby supply current vs. v cc (xtall and resonator, w atchdog timer disabled) 29.2.7 pin pull-up figure 29-78. atmega165pa: i/o pin pull-up resistor current vs. input voltage (v cc = 5v) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 1mhz_res 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0.1 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c 0 25 50 75 100 125 150 00.511.522.533.544.55 v op ( v ) i op ( u a) -45 c 374 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-79. atmega165pa: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) figure 29-80. atmega165pa: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8v) 8 5 c 0 10 20 30 40 50 60 70 8 0 0 0.5 1 1.5 2 2.5 3 v op ( v ) i op ( u a) 25 c -45 c 8 5 c 25 c 0 5 10 15 20 25 30 35 40 45 50 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v op ( v ) i op ( u a) -45 c 375 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-81. atmega165pa: reset pull-up resistor current vs. reset pin voltage (v cc = 5v) figure 29-82. atmega165pa: reset pull-up resistor current vs. reset pin voltage (v cc = 2.7v) 8 5 c 25 c -45 c 0 20 40 60 8 0 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset ( v ) i reset ( u a) 8 5 c 25 c -45 c 0 10 20 30 40 50 60 0 0.5 1 1.5 2 2.5 3 v reset ( v ) i reset ( u a) 376 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-83. atmega165pa: reset pull-up resistor current vs. reset pin voltage (v cc = 1.8v) 29.2.8 pin driver strength figure 29-84. atmega165pa: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =5v) 8 5 c 25 c -45 c 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v reset ( v ) i reset ( u a) 8 5 c 25 c -45 c 4.55 4.6 4.65 4.7 4.75 4. 8 4. 8 5 4.9 4.95 5 5.05 01234567 8 910 i oh (ma) v oh ( v ) 377 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-85. atmega165pa: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =2.7v) figure 29-86. atmega165pa: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =1.8v) 85 c 25 c -45 c 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 0246810 i oh (ma) v oh (v) 8 5 c 25 c -45 c 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1. 8 1.9 0 0.5 1 1.5 2 2.5 3 3.5 4 i oh (ma) v oh ( v ) 378 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-87. atmega165pa: i/o pin output voltage vs. source current, port b (v cc = 5v) figure 29-88. atmega165pa: i/o pin output voltage vs. source current, port b (v cc = 2.7v) 8 5 c 25 c -45 c 4.3 4.4 4.5 4.6 4.7 4. 8 4.9 5 5.1 0246 8 10 12 14 16 1 8 20 i oh (ma) v oh ( v ) 8 5 c 25 c -45 c 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 2.6 2. 8 0246 8 10 12 14 16 1 8 20 i oh (ma) v oh ( v ) 379 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-89. atmega165pa: i/o pin output voltage vs. source current, port b (v cc = 1.8v) figure 29-90. atmega165pa: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 5v) 85 c 25 c -45 c 1.3 1.4 1.5 1.6 1.7 1.8 1.9 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i oh (ma) v oh (v) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 01234567 8 910 i ol (ma) v ol ( v ) 380 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-91. atmega165pa: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 2.7v) figure 29-92. atmega165pa: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 1.8v) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 1.1 01234567 8 910 i ol (ma) v ol ( v ) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 3 i ol (ma) v ol ( v ) 381 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-93. atmega165pa: i/o pin output voltage vs. sink current, port b (v cc = 5v) figure 29-94. atmega165pa: i/o pin output voltage vs. sink current, port b (v cc = 2.7v) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol ( v ) 8 5 c 25 c -45 c 0 0.2 0.4 0.6 0. 8 1 1.2 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol ( v ) 382 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-95. atmega165pa: i/o pin output voltage vs. sink current, port b (v cc = 1.8v) 29.2.9 pin thresholds and hysteresis figure 29-96. atmega165pa: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0123456 i ol (ma) v ol ( v ) 85 c 25 c -45 c 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) thre s hold (v) 383 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-97. atmega165pa: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 29-98. atmega165pa: i/o pin input hysteresis vs. v cc 8 5 c 25 c -45 c 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 85 c 25 c -45 c 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (mv) 384 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-99. atmega165pa: reset input threshold voltage vs. v cc (v ih ,reset pin read as ?1?) figure 29-100. atmega165pa: reset input threshold voltage vs. v cc (v il ,reset pin read as ?0?) 8 5 c 25 c -45 c 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -45 c 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 385 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-101. atmega165pa: reset input pin hysteresis vs. v cc 29.2.10 bod thresholds and analog comparator offset figure 29-102. atmega165pa: bod thresholds vs. temperature (bod level is 4.3v) 85 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) rising v cc falling v cc 4.23 4.25 4.27 4.29 4.31 4.33 4.35 4.37 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) 386 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-103. atmega165pa: bod thresholds vs. temperature (bod level is 2.7v) figure 29-104. atmega165pa: bod thresholds vs. temperature (bod level is 1.8v) rising v cc falling v cc 2.662 2.677 2.692 2.707 2.722 2.737 2.752 2.767 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) rising v cc falling v cc 1.7 8 6 1.791 1.796 1. 8 01 1. 8 06 1. 8 11 1. 8 16 1. 8 21 1. 8 26 1. 8 31 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) 387 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-105. atmega165pa: bandgap voltage vs. v cc figure 29-106. atmega165pa: bandgap voltage vs. temperature 8 5 c 25 c -45 c 1.065 1.07 1.075 1.0 8 1.0 8 5 1.09 1.095 1.1 1.105 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) bandgap v oltage ( v ) 5.5 v 4.0 v 2.7 v 1. 8 v 1.067 1.072 1.077 1.0 8 2 1.0 8 7 1.092 1.097 1.102 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bandgap v oltage ( v ) 388 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-107. atmega165pa: analog comparator offset voltage vs. common mode voltage (v cc = 5v) figure 29-108. atmega165pa: analog comparator offset voltage vs. common mode voltage (v cc =2.7v) 8 5 c 25 c -40 c 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 common mode v oltage ( v ) comparator offset v oltage ( v ) 8 5 c 25 c -40 c 0 0.0005 0.001 0.0015 0.002 0.0025 0.003 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 common mode v oltage ( v ) comparator offset v oltage ( v ) 389 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.2.11 internal oscillator speed figure 29-109. atmega165a: w atchdog oscillator frequency vs. v cc figure 29-110. atmega165pa: w atchdog oscillator frequ ency vs. temperature 8 5 c 25 c -45 c 1000 1050 1100 1150 1200 1250 1300 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) f rc (khz) 5.5 v 5.0 v 4.5 v 4.0 v 3.0 v 2.7 v 1. 8 v 1000 1050 1100 1150 1200 1250 1300 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re (c) f rc (khz) 390 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-111. atmega165pa: calibrated 8mhz rc o scillator frequency vs. temperature figure 29-112. atmega165pa: calibrated 8mhz rc oscillator frequency vs. v cc 5.5 v 4.5 v 3.3 v 1. 8 v 7.5 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 -50 -30 -10 10 30 50 70 90 temperat u re (c) f rc (mhz) 8 5 c 25 c -45 c 7.5 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) f rc (mhz) 391 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-113. atmega165pa: calibrated 8mhz rc o scillator frequency vs. osccal value 29.2.12 current consumption of peripheral units figure 29-114. atmega165pa: brownout detector current vs. v cc 8 5 c -45 c 0 2 4 6 8 10 12 14 16 016324 8 64 8 0 96 112 12 8 144 160 176 192 20 8 224 240 256 osccal (x1) f rc (mhz) 25 c 8 5 c 25 c -45 c 12 16 20 24 2 8 32 36 40 44 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 392 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-115. atmega165pa: active supply current with adc at 50khz vs. v cc figure 29-116. atmega165pa: active supply current with adc at 200khz vs. v cc 85 c 25 c -45 c 150 175 200 225 250 275 300 325 350 375 400 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc ( u a) 85 c 25 c -45 c 150 175 200 225 250 275 300 325 350 375 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc ( u a) 393 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-117. atmega165a: active supply current with adc at 1mhz vs. v cc figure 29-118. atmega165pa: aref external reference current vs. v cc 85 c 25 c -45 c 125 150 175 200 225 250 275 300 325 350 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc ( u a) 85 c 25 c -45 c 40 60 80 100 120 140 160 180 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc ( u a) 394 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-119. atmega165a: w atchdog timer current vs. v cc figure 29-120. atmega165pa: analog comparator current vs. v cc 8 5 c 25 c -45 c 0 5 10 15 20 25 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 85 c 25 c -45 c 30 35 40 45 50 55 60 65 70 75 80 85 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc ( u a) 395 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-121. atmega165pa: programming current vs. v cc 29.2.13 current consumption in reset and reset pulsewidth figure 29-122. atmega165pa: reset supply current vs. v cc (0.1 - 1.0mhz, excluding current through the reset pull-up) 8 5 c 25 c -45 c 0 2 4 6 8 10 12 14 16 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 396 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-123. atmega165pa: reset supply current vs. v cc (1 - 16mhz, excluding current through the reset pull-up) figure 29-124. atmega165pa: minimum reset pulse w idth vs. v cc 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 0246 8 10 12 14 16 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 8 5 c 25 c -45 c 0 400 8 00 1200 1600 2000 2400 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) p u lse w idth (ns) 397 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.3 atmega325a 29.3.1 active supply current figure 29-125. atmega325a: active supply current vs. frequency (0.1 - 1.0mhz) figure 29-126. atmega325a: active supply current vs. frequency (1 - 20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre qu ency [mhz] i cc [ma] 5.5 v 5.0 v 4.5 v 0 2 4 6 8 10 12 14 0 2 4 6 8 101214161820 fre qu ency [mhz] i cc [ma] 4.0 v 3.3 v 2.7 v 1.8 v 398 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-127. atmega325a: active supply current vs. v cc (internal rc oscillator, 8mhz figure 29-128. atmega325a: active supply current vs. v cc (internal rc os cillator, 1mhz) 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 399 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-129. atmega325a: active supply current vs. v cc (32khz w atch crystal) 29.3.2 idle supply current figure 29-130. atmega325a: idle supply current vs. frequency (0.1 - 1.0mhz) 85 c 25 c -40 c 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1.522.533.544.555.5 v cc [v] i cc [ma] 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency [mhz] i cc [ma] 400 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-131. atmega325a: idle supply current vs. frequency (1 - 20mhz) figure 29-132. atmega325a: idle supply current vs. v cc (internal rc oscillator, 8mhz) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0246 8 10 12 14 16 1 8 20 fre qu ency [mhz] i cc [ma] 4.0 v 4.5 v 2.7 v 3.3 v 1. 8 v 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 401 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-133. atmega325a: idle supply current vs. v cc (internal rc oscillator, 1 mhz) figure 29-134. atmega325a: idle supply current vs. v cc (32khz w atch crystal) 29.3.3 atmega325a : supply current of i/o modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 8 5 c 25 c -40 c 1 2 3 4 5 6 7 8 9 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 402 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 are controlled by the power reduction register. see ?power reduction register? on page 41 for details. it is possible to calculate the typical current consumption based on the numbers from table 29-2 for other v cc and frequency settings than listed in table 29-1 . 29.3.3.1 example 1 calculate the expected current consumption in idle mode with usart0, timer1, and spi enabled at v cc = 3.0v and f = 1mhz. from table 29-2 , second column, we see that we need to add 13.1% for the usart0, 13.0% for the spi, and 13.2% for the timer1 module. reading from figure 29-6 , we find that the idle current consumption is ~0.09 ma at v cc = 3.0v and f = 1mhz. the total current consumption in idle mode with usart0, timer1, and spi enabled, gives: table 29-5. atmega325a: additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz pradc 7 a 44 a 195 a prusart0 6.9 a 43.5 a 210 a prspi 6.6 a 47 a 205 a prtim1 7 a 47 a 206 a table 29-6. atmega325a: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 29-1 and figure 29-2 ) additional current consumption compared to idle with external clock (see figure 29-6 and figure 29-7 ) pradc 3.2% 12.7% prusart0 3.4% 13.1% prspi 3.3% 13.0% prtim1 3.4% 13.2% i cc total 0.09 ma 1 0.131 0.13 0.132 +++ () ? 0.13 ma ? 403 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.3.4 power-down supply current figure 29-135. atmega325a: power-down supply current vs. v cc ( w atchdog timer disabled) figure 29-136. atmega325a: power-down supply current vs. v cc ( w atchdog timer enabled) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc [v] i cc [ u a] 85 c 25 c -40 c 2 4 6 8 10 12 14 16 18 20 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc [v] i cc [ u a] 404 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.3.5 power-save supply current figure 29-137. atmega325a: power-save supply current vs. v cc ( w atchdog timer disabled and 32khz crystal oscillator running) the differential current consumption between power-save with w d disabled and 32khz tosc represents the current drawn by timer/counter2. 29.3.6 standby supply current figure 29-138. atmega325a: standby supply current vs. v cc (32khz w atch crystal, w atchdog timer disabled) 85 c 25 c -40 c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ma] 85 c 25 c -40 c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ma] 405 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-139. atmega325a: standby supply current vs. v cc (xtall and resonator, w atchdog timer disabled) 29.3.7 pin pull-up figure 29-140. atmega325a: i/o pin pull-up resistor current vs. input voltage (v cc = 5v) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 1mhz_res 0.01 0.03 0.05 0.07 0.09 0.11 0.13 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 85 c 25 c -40 c 0 20 40 60 80 100 120 140 160 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v op [v] i op [ u a] 406 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-141. atmega325a: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) figure 29-142. atmega325a: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8v) 85 c 25 c -40 c 0 10 20 30 40 50 60 70 80 90 0 0.5 1 1.5 2 2.5 3 v op [v] i op [ u a] 85 c 25 c -40 c 0 10 20 30 40 50 60 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v op [v] i op [ u a] 407 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-143. atmega325a: reset pull-up resistor current vs. reset pin voltage (v cc = 5v) figure 29-144. atmega325a: reset pull-up resistor current vs. reset pin voltage (v cc = 2.7v) 85 c 25 c -40 c 0 20 40 60 80 100 120 140 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset [v] i reset [ u a] 85 c 25 c -40 c 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 2.5 3 v reset [v] i reset [ u a] 408 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-145. atmega325a: reset pull-up resistor current vs. reset pin voltage (v cc = 1.8v) 29.3.8 pin driver strength figure 29-146. atmega325a: i/o pin output voltage vs. sour ce current, ports a, c, d, e, f, g (v cc =5v) 85 c 25 c -40 c 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v reset [v] i reset [ u a] 85 c 25 c -40 c 4.6 4.65 4.7 4.75 4.8 4.85 4.9 4.95 5 5.05 012345678910 i oh [ma] v oh [v] 409 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-147. atmega325a: i/o pin output voltage vs. sour ce current, ports a, c, d, e, f, g (v cc =2.7v) figure 29-148. atmega325a: i/o pin output voltage vs. sour ce current, ports a, c, d, e, f, g (v cc =1.8v) 85 c 25 c -40 c 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 012345678910 i oh [ma] v oh [v] 85 c 25 c -40 c 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 0 0.5 1 1.5 2 2.5 3 3.5 4 i oh [ma] v oh [v] 410 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-149. atmega325a: i/o pin output voltage vs. source current, port b (v cc = 5v) figure 29-150. atmega325a: i/o pin output voltage vs. source current, port b (v cc = 2.7v) 85c 25c -40c 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 5.1 0 2 4 6 8 10 12 14 16 18 20 i oh [ma] v oh [v] 85c 25c -40c 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 02468101214161820 i oh [ma] v oh [v] 411 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-151. atmega325a: i/o pin output voltage vs. source current, port b (v cc = 1.8v) figure 29-152. atmega325a: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 5v) 85c 25c -40c 1.3 1.4 1.5 1.6 1.7 1.8 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i oh [ma] v oh [v] 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 012345678910 i ol [ma] v ol [v] 412 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-153. atmega325a: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 2.7v) figure 29-154. atmega325a: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 1.8v) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 012345678910 i ol [ma] v ol [v] 85 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 i ol [ma] v ol [v] 413 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-155. atmega325a: i/o pin output voltage vs. sink current, port b (v cc = 5v) figure 29-156. atmega325a: i/o pin output voltage vs. sink current, port b (v cc = 2.7v) 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 02468101214161820 i ol [ma] v ol [v] 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 0 2 4 6 8 10 12 14 16 18 20 i ol [ma] v ol [v] 414 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-157. atmega325a: i/o pin output voltage vs. sink current, port b (v cc = 1.8v) 29.3.9 pin thresholds and hysteresis figure 29-158. atmega325a: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 85c 25c -40c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 i ol [ma] v ol [v] 8 5 c 25 c -40 c 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 415 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-159. atmega325a: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 29-160. atmega325a: i/o pin input hysteresis vs. v cc 8 5 c 25 c -40 c 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -40 c 0.25 0.29 0.33 0.37 0.41 0.45 0.49 0.53 0.57 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis (m v ) 416 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-161. atmega325a: reset input threshold voltage vs. v cc (v ih ,reset pin read as ?1?) figure 29-162. atmega325a: reset input threshold voltage vs. v cc (v il ,reset pin read as ?0?) 85 c 25 c -40 c 1 1.2 1.4 1.6 1.8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) thre s hold (v) 85 c 25 c -40 c 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) thre s hold (v) 417 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-163. atmega325a: reset input pin hysteresis vs. v cc 29.3.10 bod thresholds and analog comparator offset figure 29-164. atmega325a: bod thresholds vs. temperature (bod level is 4.3v) 8 5 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis (m v ) rising v cc falling v cc 4.225 4.25 4.275 4.3 4.325 4.35 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] bod threshold [ v ] 418 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-165. atmega325a: bod thresholds vs. temperature (bod level is 2.7v) figure 29-166. atmega325a: bod thresholds vs. temperature (bod level is 1.8v) rising v cc falling v cc 2.65 2.675 2.7 2.725 2.75 2.775 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] bod threshold [ v ] rising v cc falling v cc 1.7 8 5 1.795 1. 8 05 1. 8 15 1. 8 25 1. 8 35 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] bod threshold [ v ] 419 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-167. atmega325a: bandgap voltage vs. v cc figure 29-168. atmega325a: bandgap voltage vs. temperature 85 c 25 c -40 c 1.08 1.085 1.09 1.095 1.1 1.105 1.11 1.115 1.12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 vcc [v] b a ndg a p volt a ge [v] 5.5 v 4.0 v 2.7 v 1. 8 v 1.0 8 5 1.09 1.095 1.1 1.105 1.11 1.115 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] bandgap v oltage [ v ] 420 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.3.11 internal oscillator speed figure 29-169. atmega325a: w atchdog oscillator frequency vs. v cc figure 29-170. atmega325a: w atchdog oscillator frequ ency vs. temperature 85c 25c -40c 1000 1025 1050 1075 1100 1125 1150 1175 1200 1225 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] f rc [khz] 5.5 v 5.0 v 4.5 v 4.0 v 3.0 v 2.7 v 1. 8 v 1000 1050 1100 1150 1200 1250 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 0 temperat u re [c] f rc [khz] 421 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-171. atmega325a: calibrated 8m hz rc oscillator freq uency vs. temperature figure 29-172. atmega325a: calibrate d 8mhz rc oscillato r frequency vs. v cc 5.5 v 4.5 v 3.3 v 2.7 v 1. 8 v 7.4 7.5 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 8 .3 -40 -20 0 20 40 60 8 0 temperat u re [c] f rc [mhz] 85 c 25 c -40 c 7.4 7.5 7.6 7.7 7.8 7.9 8 8.1 8.2 8.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] f rc [mhz] 422 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-173. atmega325a: calibrated 8m hz rc oscillator freq uency vs. osccal value 29.3.12 current consumption of peripheral units figure 29-174. atmega325a: brownout detector current vs. v cc 0 2 4 6 8 10 12 14 16 016324 8 64 8 09611212 8 144 160 176 192 20 8 224 240 256 osccal [x1] f rc [mhz] -40 c 8 5 c 25 c 85 c 25 c -40 c 10 15 20 25 30 35 40 45 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 423 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-175. atmega325a: active supply current with adc at 50khz vs. v cc figure 29-176. atmega325a: active supply current with adc at 200khz vs. v cc 85 c 25 c -40 c 150 175 200 225 250 275 300 325 350 375 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 85 c 25 c -40 c 125 150 175 200 225 250 275 300 325 350 375 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 424 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-177. atmega325a: active supply current with adc at 1mhz vs. v cc figure 29-178. atmega325a: aref external reference current vs. v cc 85 c 25 c -40 c 125 150 175 200 225 250 275 300 325 350 375 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 85 c 25 c -40 c 20 40 60 80 100 120 140 160 180 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 425 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-179. atmega325a: w atchdog timer current vs. v cc figure 29-180. atmega325a: analog comparator current vs. v cc 85 c 25 c -40 c 0 2.5 5 7.5 10 12.5 15 17.5 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 85 c 25 c -40 c 30 40 50 60 70 80 90 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 426 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-181. atmega325a: programming current vs. v cc 29.3.13 current consumption in reset and reset pulsewidth figure 29-182. atmega325a: reset supply current vs. v cc (0.1 - 1.0mhz, excluding current through the reset pull-up) 85 c 25 c -40 c 2 4 6 8 10 12 14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ma] 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre qu ency [mhz] i cc [ma] 427 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-183. atmega325a: reset supply current vs. v cc (1 - 20mhz, excluding current through the reset pull-up) figure 29-184. atmega325a: minimum reset pulse w idth vs. v cc 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.5 1 1.5 2 2.5 0 2 4 6 8 10 12 14 16 18 20 fre qu ency [mhz] i cc [ma] 85 c 25 c -40 c 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] p u l s ewidth [n s ] 428 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.4 atmega325pa 29.4.1 active supply current figure 29-185. atmega325pa: active supply current vs. frequency (0.1 - 1.0mhz) figure 29-186. atmega325pa: active supply current vs. frequency (1 - 20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre qu ency [mhz] i cc [ma] 5.5 v 5.0 v 4.5 v 0 2 4 6 8 10 12 14 0 2 4 6 8 101214161820 fre qu ency [mhz] i cc [ma] 4.0 v 3.3 v 2.7 v 1.8 v 429 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-187. atmega325pa: active supply current vs. v cc (internal rc oscillator, 8mhz figure 29-188. atmega325pa: active supply current vs. v cc (internal rc os cillator, 1mhz) 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 430 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-189. atmega325pa: active supply current vs. v cc (32khz w atch crystal) 29.4.2 idle supply current figure 29-190. atmega325pa: idle supply current vs. frequency (0.1 - 1.0mhz) 85 c 25 c -40 c 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1.522.533.544.555.5 v cc [v] i cc [ma] 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency [mhz] i cc [ma] 431 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-191. atmega325pa: idle supply current vs. frequency (1 - 20mhz) figure 29-192. atmega325pa: idle s upply current vs. v cc (internal rc os cillator, 8mhz) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0246 8 10 12 14 16 1 8 20 fre qu ency [mhz] i cc [ma] 4.0 v 4.5 v 2.7 v 3.3 v 1. 8 v 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 432 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-193. atmega325pa: idle s upply current vs. v cc (internal rc oscillator, 1 mhz) figure 29-194. atmega325pa: idle s upply current vs. v cc (32khz w atch crystal) 29.4.3 atmega325pa: supply current of i/o modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 8 5 c 25 c -40 c 1 2 3 4 5 6 7 8 9 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 433 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 are controlled by the power reduction register. see ?power reduction register? on page 41 for details. it is possible to calculate the typical current consumption based on the numbers from table 29-8 for other v cc and frequency settings than listed in table 29-7 . 29.4.3.1 example 1 calculate the expected current consumption in idle mode with usart0, timer1, and spi enabled at v cc = 3.0v and f = 1mhz. from table 29-7 , second column, we see that we need to add 13.1% for the usart0, 13.0% for the spi, and 13.2% for the timer1 module. reading from figure 29-191 , we find that the idle current consumption is ~0.09 ma at v cc = 3.0v and f = 1mhz. the total current consumption in idle mode with usart0, timer1, and spi enabled, gives: table 29-7. atmega325pa: additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz pradc 7 a 44 a 195 a prusart0 6.9 a 43.5 a 210 a prspi 6.6 a 47 a 205 a prtim1 7 a 47 a 206 a table 29-8. atmega325pa: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 29-185 and figure 29-186 ) additional current consumption compared to idle with external clock (see figure 29-190 and figure 29-191 ) pradc 3.2% 12.7% prusart0 3.4% 13.1% prspi 3.3% 13.0% prtim1 3.4% 13.2% i cc total 0.09 ma 1 0.131 0.13 0.132 +++ () ? 0.13 ma ? 434 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.4.4 power-down supply current figure 29-195. atmega325pa: power-down supply current vs. v cc ( w atchdog timer disabled) figure 29-196. atmega325pa: power-down supply current vs. v cc ( w atchdog timer enabled) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc [v] i cc [ u a] 85 c 25 c -40 c 2 4 6 8 10 12 14 16 18 20 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc [v] i cc [ u a] 435 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.4.5 power-save supply current figure 29-197. atmega325pa: power-save supply current vs. v cc ( w atchdog timer disabled and 32khz crystal oscillator running) the differential current consumption between power-save with w d disabled and 32khz tosc represents the current drawn by timer/counter2. 29.4.6 standby supply current figure 29-198. atmega325pa: standby supply current vs. v cc (32khz w atch crystal, w atch- dog timer disabled) 85 c 25 c -40 c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ma] 85 c 25 c -40 c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ma] 436 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-199. atmega325pa: standby supply current vs. v cc (xtall and resonator, w atch- dog timer disabled) 29.4.7 pin pull-up figure 29-200. atmega325pa: i/o pin pull-up resi stor current vs. input voltage (v cc = 5v) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 1mhz_res 0.01 0.03 0.05 0.07 0.09 0.11 0.13 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 85 c 25 c -40 c 0 20 40 60 80 100 120 140 160 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v op [v] i op [ u a] 437 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-201. atmega325pa: i/o pin pull-up resi stor current vs. input voltage (v cc = 2.7v) figure 29-202. atmega325pa: i/o pin pull-up resi stor current vs. input voltage (v cc = 1.8v) 85 c 25 c -40 c 0 10 20 30 40 50 60 70 80 90 0 0.5 1 1.5 2 2.5 3 v op [v] i op [ u a] 85 c 25 c -40 c 0 10 20 30 40 50 60 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v op [v] i op [ u a] 438 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-203. atmega325pa: reset pull- up resistor current vs. reset pin voltage (v cc = 5v) figure 29-204. atmega325pa: reset pull-up resistor current vs. reset pin voltage (v cc = 2.7v) 85 c 25 c -40 c 0 20 40 60 80 100 120 140 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset [v] i reset [ u a] 85 c 25 c -40 c 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 2.5 3 v reset [v] i reset [ u a] 439 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-205. atmega325pa: reset pull-up resistor current vs. reset pin voltage (v cc = 1.8v) 29.4.8 pin driver strength figure 29-206. atmega325pa: i/o pin output voltage vs. so urce current, ports a, c, d, e, f, g (v cc =5v) 85 c 25 c -40 c 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v reset [v] i reset [ u a] 85 c 25 c -40 c 4.6 4.65 4.7 4.75 4.8 4.85 4.9 4.95 5 5.05 012345678910 i oh [ma] v oh [v] 440 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-207. atmega325pa: i/o pin output voltage vs. so urce current, ports a, c, d, e, f, g (v cc =2.7v) figure 29-208. atmega325pa: i/o pin output voltage vs. so urce current, ports a, c, d, e, f, g (v cc =1.8v) 85 c 25 c -40 c 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 012345678910 i oh [ma] v oh [v] 85 c 25 c -40 c 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 0 0.5 1 1.5 2 2.5 3 3.5 4 i oh [ma] v oh [v] 441 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-209. atmega325pa: i/o pin output voltage vs. source curr ent, port b (v cc = 5v) figure 29-210. atmega325pa: i/o pin output voltage vs. source curr ent, port b (v cc = 2.7v) 85c 25c -40c 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 5.1 0 2 4 6 8 10 12 14 16 18 20 i oh [ma] v oh [v] 85c 25c -40c 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 02468101214161820 i oh [ma] v oh [v] 442 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-211. atmega325pa: i/o pin output voltage vs. source curr ent, port b (v cc = 1.8v) figure 29-212. atmega325pa: i/o pin output voltage vs. si nk current, ports a, c, d, e, f, g (v cc = 5v) 85c 25c -40c 1.3 1.4 1.5 1.6 1.7 1.8 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i oh [ma] v oh [v] 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 012345678910 i ol [ma] v ol [v] 443 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-213. atmega325pa: i/o pin output voltage vs. si nk current, ports a, c, d, e, f, g (v cc = 2.7v) figure 29-214. atmega325pa: i/o pin output voltage vs. si nk current, ports a, c, d, e, f, g (v cc = 1.8v) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 012345678910 i ol [ma] v ol [v] 85 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 i ol [ma] v ol [v] 444 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-215. atmega325pa: i/o pin output voltage vs. sink current, port b (v cc = 5v) figure 29-216. atmega325a: i/o pin output voltage vs. sink current, port b (v cc = 2.7v) 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 02468101214161820 i ol [ma] v ol [v] 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 0 2 4 6 8 10 12 14 16 18 20 i ol [ma] v ol [v] 445 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-217. atmega325pa: i/o pin output voltage vs. sink current, port b (v cc = 1.8v) 29.4.9 pin thresholds and hysteresis figure 29-218. atmega325pa: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 85c 25c -40c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 i ol [ma] v ol [v] 8 5 c 25 c -40 c 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 446 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-219. atmega325pa: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 29-220. atmega325pa: i/o pin input hysteresis vs. v cc 8 5 c 25 c -40 c 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -40 c 0.25 0.29 0.33 0.37 0.41 0.45 0.49 0.53 0.57 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis (m v ) 447 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-221. atmega325pa: reset input threshold voltage vs. v cc (v ih ,reset pin read as ?1?) figure 29-222. atmega325pa: reset input threshold voltage vs. v cc (v il ,reset pin read as ?0?) 85 c 25 c -40 c 1 1.2 1.4 1.6 1.8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) thre s hold (v) 85 c 25 c -40 c 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) thre s hold (v) 448 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-223. atmega325pa: reset input pin hysteresis vs. v cc 29.4.10 bod thresholds and analog comparator offset figure 29-224. atmega325pa: bod thresholds vs. temperature (bod level is 4.3v) 8 5 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis (m v ) rising v cc falling v cc 4.225 4.25 4.275 4.3 4.325 4.35 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] bod threshold [ v ] 449 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-225. atmega325pa: bod thresholds vs. temperature (bod level is 2.7v) figure 29-226. atmega325pa: bod thresholds vs. temperature (bod level is 1.8v) rising v cc falling v cc 2.65 2.675 2.7 2.725 2.75 2.775 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] bod threshold [ v ] rising v cc falling v cc 1.7 8 5 1.795 1. 8 05 1. 8 15 1. 8 25 1. 8 35 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] bod threshold [ v ] 450 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-227. atmega325pa: bandgap voltage vs. v cc figure 29-228. atmega325pa: bandgap voltage vs. temperature 85 c 25 c -40 c 1.08 1.085 1.09 1.095 1.1 1.105 1.11 1.115 1.12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 vcc [v] b a ndg a p volt a ge [v] 5.5 v 4.0 v 2.7 v 1. 8 v 1.0 8 5 1.09 1.095 1.1 1.105 1.11 1.115 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] bandgap v oltage [ v ] 451 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.4.11 internal oscillator speed figure 29-229. atmega325pa: w atchdog oscillator frequency vs. v cc figure 29-230. atmega325pa: w atchdog oscillator frequ ency vs. temperature 85c 25c -40c 1000 1025 1050 1075 1100 1125 1150 1175 1200 1225 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] f rc [khz] 5.5 v 5.0 v 4.5 v 4.0 v 3.0 v 2.7 v 1. 8 v 1000 1050 1100 1150 1200 1250 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 0 temperat u re [c] f rc [khz] 452 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-231. atmega325pa: calibrated 8mhz rc o scillator frequency vs. temperature figure 29-232. atmega325pa: calibrated 8mhz rc oscillator frequency vs. v cc 5.5 v 4.5 v 3.3 v 2.7 v 1. 8 v 7.4 7.5 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 8 .3 -40 -20 0 20 40 60 8 0 temperat u re [c] f rc [mhz] 85 c 25 c -40 c 7.4 7.5 7.6 7.7 7.8 7.9 8 8.1 8.2 8.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] f rc [mhz] 453 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-233. atmega325pa: calibrated 8mhz rc o scillator frequency vs. osccal value 29.4.12 current consumption of peripheral units figure 29-234. atmega325pa: brownout detector current vs. v cc 0 2 4 6 8 10 12 14 16 016324 8 64 8 09611212 8 144 160 176 192 20 8 224 240 256 osccal [x1] f rc [mhz] -40 c 8 5 c 25 c 85 c 25 c -40 c 10 15 20 25 30 35 40 45 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 454 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-235. atmega325pa: active supply current with adc at 50khz vs. v cc figure 29-236. atmega325pa: active supply current with adc at 200khz vs. v cc 85 c 25 c -40 c 150 175 200 225 250 275 300 325 350 375 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 85 c 25 c -40 c 125 150 175 200 225 250 275 300 325 350 375 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 455 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-237. atmega325pa: active supply current with adc at 1mhz vs. v cc figure 29-238. atmega325pa: aref external reference current vs. v cc 85 c 25 c -40 c 125 150 175 200 225 250 275 300 325 350 375 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 85 c 25 c -40 c 20 40 60 80 100 120 140 160 180 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 456 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-239. atmega325pa: w atchdog timer current vs. v cc figure 29-240. atmega325pa: analog comparator current vs. v cc 85 c 25 c -40 c 0 2.5 5 7.5 10 12.5 15 17.5 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 85 c 25 c -40 c 30 40 50 60 70 80 90 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 457 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-241. atmega325pa: programming current vs. v cc 29.4.13 current consumption in reset and reset pulsewidth figure 29-242. atmega325pa: reset supply current vs. v cc (0.1 - 1.0mhz, excluding current through the reset pull-up) 85 c 25 c -40 c 2 4 6 8 10 12 14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ma] 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre qu ency [mhz] i cc [ma] 458 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-243. atmega325pa: reset supply current vs. v cc (1 - 20mhz, excluding current through the reset pull-up) figure 29-244. atmega325pa: minimum reset pulse w idth vs. v cc 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.5 1 1.5 2 2.5 0 2 4 6 8 10 12 14 16 18 20 fre qu ency [mhz] i cc [ma] 85 c 25 c -40 c 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] p u l s ewidth [n s ] 459 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.5 atmega3250a 29.5.1 active supply current figure 29-245. atmega3250a: active supply current vs. frequency (0.1 - 1.0mhz) figure 29-246. atmega3250a: active supply current vs. frequency (1 - 20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre qu ency [mhz] i cc [ma] 5.5 v 5.0 v 4.5 v 0 2 4 6 8 10 12 14 0 2 4 6 8 101214161820 fre qu ency [mhz] i cc [ma] 4.0 v 3.3 v 2.7 v 1.8 v 460 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-247. atmega3250a: active supply current vs. v cc (internal rc o scillator, 8mhz figure 29-248. atmega3250a: active supply current vs. v cc (internal rc o scillator, 1mhz) 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 461 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-249. atmega3250a: active supply current vs. v cc (32khz w atch crystal) 29.5.2 idle supply current figure 29-250. atmega3250a: idle supply current vs. frequency (0.1 - 1.0mhz) 85 c 25 c -40 c 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1.522.533.544.555.5 v cc [v] i cc [ma] 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency [mhz] i cc [ma] 462 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-251. atmega3250a: idle supply current vs. frequency (1 - 20mhz) figure 29-252. atmega3250a: idle su pply current vs. v cc (internal rc o scillator, 8mhz) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0246 8 10 12 14 16 1 8 20 fre qu ency [mhz] i cc [ma] 4.0 v 4.5 v 2.7 v 3.3 v 1. 8 v 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 463 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-253. atmega3250a: idle su pply current vs. v cc (internal rc o scillator, 1 mhz) figure 29-254. atmega3250a: idle su pply current vs. v cc (32khz w atch crystal) 29.5.3 atmega3250a : supply current of i/o modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 8 5 c 25 c -40 c 1 2 3 4 5 6 7 8 9 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 464 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 are controlled by the power reduction register. see ?power reduction register? on page 41 for details. it is possible to calculate the typical current consumption based on the numbers from table 29- 10 for other v cc and frequency settings than listed in table 29-9 . 29.5.3.1 example 1 calculate the expected current consumption in idle mode with usart0, timer1, and spi enabled at v cc = 3.0v and f = 1mhz. from table 29-9 , second column, we see that we need to add 13.1% for the usart0, 13.0% for the spi, and 13.2% for the timer1 module. reading from figure 29-251 , we find that the idle current consumption is ~0.09 ma at v cc = 3.0v and f = 1mhz. the total current consumption in idle mode with usart0, timer1, and spi enabled, gives: table 29-9. atmega3250a: additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz pradc 7 a 44 a 195 a prusart0 6.9 a 43.5 a 210 a prspi 6.6 a 47 a 205 a prtim1 7 a 47 a 206 a table 29-10. atmega3250a: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 29-245 and figure 29-246 ) additional current consumption compared to idle with external clock (see figure 29-250 and figure 29-251 ) pradc 3.2% 12.7% prusart0 3.4% 13.1% prspi 3.3% 13.0% prtim1 3.4% 13.2% i cc total 0.09 ma 1 0.131 0.13 0.132 +++ () ? 0.13 ma ? 465 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.5.4 power-down supply current figure 29-255. atmega3250a: power-down supply current vs. v cc ( w atchdog timer disabled) figure 29-256. atmega3250a: power-down supply current vs. v cc ( w atchdog timer enabled) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc [v] i cc [ u a] 85 c 25 c -40 c 2 4 6 8 10 12 14 16 18 20 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc [v] i cc [ u a] 466 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.5.5 power-save supply current figure 29-257. atmega3250a: power-save supply current vs. v cc ( w atchdog timer disabled and 32khz crystal oscillator running) the differential current consumption between power-save with w d disabled and 32khz tosc represents the current drawn by timer/counter2. 29.5.6 standby supply current figure 29-258. atmega3250a: standby supply current vs. v cc (32khz w atch crystal, w atch- dog timer disabled) 85 c 25 c -40 c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ma] 85 c 25 c -40 c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ma] 467 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-259. atmega3250a: standby supply current vs. v cc (xtall and resonator, w atchdog timer disabled) 29.5.7 pin pull-up figure 29-260. atmega3250a: i/o pin pull-up resistor current vs. input voltage (v cc = 5v) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 1mhz_res 0.01 0.03 0.05 0.07 0.09 0.11 0.13 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 85 c 25 c -40 c 0 20 40 60 80 100 120 140 160 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v op [v] i op [ u a] 468 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-261. atmega3250a: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) figure 29-262. atmega3250a: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8v) 85 c 25 c -40 c 0 10 20 30 40 50 60 70 80 90 0 0.5 1 1.5 2 2.5 3 v op [v] i op [ u a] 85 c 25 c -40 c 0 10 20 30 40 50 60 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v op [v] i op [ u a] 469 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-263. atmega3250a: reset pull-up resistor current vs. reset pin voltage (v cc = 5v) figure 29-264. atmega3250a: reset pull-up resist or current vs. reset pin voltage (v cc = 2.7v) 85 c 25 c -40 c 0 20 40 60 80 100 120 140 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset [v] i reset [ u a] 85 c 25 c -40 c 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 2.5 3 v reset [v] i reset [ u a] 470 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-265. atmega3250a: reset pull-up resistor current vs. reset pin voltage (v cc = 1.8v) 29.5.8 pin driver strength figure 29-266. atmega3250a: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =5v) 85 c 25 c -40 c 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v reset [v] i reset [ u a] 85 c 25 c -40 c 4.6 4.65 4.7 4.75 4.8 4.85 4.9 4.95 5 5.05 012345678910 i oh [ma] v oh [v] 471 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-267. atmega3250a: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =2.7v) figure 29-268. atmega3250a: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =1.8v) 85 c 25 c -40 c 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 012345678910 i oh [ma] v oh [v] 85 c 25 c -40 c 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 0 0.5 1 1.5 2 2.5 3 3.5 4 i oh [ma] v oh [v] 472 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-269. atmega3250a: i/o pin output voltage vs. source current, port b (v cc = 5v) figure 29-270. atmega3250a: i/o pin output voltage vs. source current, port b (v cc = 2.7v) 85c 25c -40c 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 5.1 0 2 4 6 8 10 12 14 16 18 20 i oh [ma] v oh [v] 85c 25c -40c 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 02468101214161820 i oh [ma] v oh [v] 473 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-271. atmega3250a: i/o pin output voltage vs. source current, port b (v cc = 1.8v) figure 29-272. atmega3250a: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 5v) 85c 25c -40c 1.3 1.4 1.5 1.6 1.7 1.8 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i oh [ma] v oh [v] 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 012345678910 i ol [ma] v ol [v] 474 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-273. atmega3250a: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 2.7v) figure 29-274. atmega3250a: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 1.8v) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 012345678910 i ol [ma] v ol [v] 85 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 i ol [ma] v ol [v] 475 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-275. atmega3250a: i/o pin output voltage vs. sink current, port b (v cc = 5v) figure 29-276. atmega3250a: i/o pin output voltage vs. sink current, port b (v cc = 2.7v) 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 02468101214161820 i ol [ma] v ol [v] 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 0 2 4 6 8 10 12 14 16 18 20 i ol [ma] v ol [v] 476 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-277. atmega3250a: i/o pin output voltage vs. sink current, port b (v cc = 1.8v) 29.5.9 pin thresholds and hysteresis figure 29-278. atmega3250a: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 85c 25c -40c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 i ol [ma] v ol [v] 8 5 c 25 c -40 c 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 477 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-279. atmega3250a: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 29-280. atmega3250a: i/o pin input hysteresis vs. v cc 8 5 c 25 c -40 c 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -40 c 0.25 0.29 0.33 0.37 0.41 0.45 0.49 0.53 0.57 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis (m v ) 478 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-281. atmega3250a: reset input threshold voltage vs. v cc (v ih ,reset pin read as ?1?) figure 29-282. atmega3250a: reset input threshold voltage vs. v cc (v il ,reset pin read as ?0?) 85 c 25 c -40 c 1 1.2 1.4 1.6 1.8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) thre s hold (v) 85 c 25 c -40 c 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) thre s hold (v) 479 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-283. atmega3250a: reset input pin hysteresis vs. v cc 29.5.10 bod thresholds and analog comparator offset figure 29-284. atmega3250a: bod thresholds vs. temperature (bod level is 4.3v) 8 5 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis (m v ) rising v cc falling v cc 4.225 4.25 4.275 4.3 4.325 4.35 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] bod threshold [ v ] 480 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-285. atmega3250a: bod thresholds vs. temperature (bod level is 2.7v) figure 29-286. atmega3250a: bod thresholds vs. temperature (bod level is 1.8v) rising v cc falling v cc 2.65 2.675 2.7 2.725 2.75 2.775 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] bod threshold [ v ] rising v cc falling v cc 1.7 8 5 1.795 1. 8 05 1. 8 15 1. 8 25 1. 8 35 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] bod threshold [ v ] 481 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-287. atmega3250a: bandgap voltage vs. v cc figure 29-288. atmega3250a: bandgap voltage vs. temperature 85 c 25 c -40 c 1.08 1.085 1.09 1.095 1.1 1.105 1.11 1.115 1.12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 vcc [v] b a ndg a p volt a ge [v] 5.5 v 4.0 v 2.7 v 1. 8 v 1.0 8 5 1.09 1.095 1.1 1.105 1.11 1.115 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] bandgap v oltage [ v ] 482 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.5.11 internal oscillator speed figure 29-289. atmega3250a: w atchdog oscillator frequency vs. v cc figure 29-290. atmega3250a: w atchdog oscillator freq uency vs. temperature 85c 25c -40c 1000 1025 1050 1075 1100 1125 1150 1175 1200 1225 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] f rc [khz] 5.5 v 5.0 v 4.5 v 4.0 v 3.0 v 2.7 v 1. 8 v 1000 1050 1100 1150 1200 1250 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 0 temperat u re [c] f rc [khz] 483 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-291. atmega3250a: calibrated 8mhz rc os cillator frequency vs. temperature figure 29-292. atmega3250a: calibrated 8mhz rc oscillator frequency vs. v cc 5.5 v 4.5 v 3.3 v 2.7 v 1. 8 v 7.4 7.5 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 8 .3 -40 -20 0 20 40 60 8 0 temperat u re [c] f rc [mhz] 85 c 25 c -40 c 7.4 7.5 7.6 7.7 7.8 7.9 8 8.1 8.2 8.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] f rc [mhz] 484 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-293. atmega3250a: calibrated 8mhz rc osc illator frequency vs. osccal value 29.5.12 current consumption of peripheral units figure 29-294. atmega3250a: brownout detector current vs. v cc 0 2 4 6 8 10 12 14 16 016324 8 64 8 09611212 8 144 160 176 192 20 8 224 240 256 osccal [x1] f rc [mhz] -40 c 8 5 c 25 c 85 c 25 c -40 c 10 15 20 25 30 35 40 45 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 485 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-295. atmega3250a: active supply current with adc at 50khz vs. v cc figure 29-296. atmega3250a: active supply current with adc at 200khz vs. v cc 85 c 25 c -40 c 150 175 200 225 250 275 300 325 350 375 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 85 c 25 c -40 c 125 150 175 200 225 250 275 300 325 350 375 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 486 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-297. atmega3250a: active supply current with adc at 1mhz vs. v cc figure 29-298. atmega3250a: aref external reference current vs. v cc 85 c 25 c -40 c 125 150 175 200 225 250 275 300 325 350 375 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 85 c 25 c -40 c 20 40 60 80 100 120 140 160 180 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 487 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-299. atmega3250a: w atchdog timer current vs. v cc figure 29-300. atmega3250a: analog comparator current vs. v cc 85 c 25 c -40 c 0 2.5 5 7.5 10 12.5 15 17.5 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 85 c 25 c -40 c 30 40 50 60 70 80 90 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 488 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-301. atmega3250a: programming current vs. v cc 29.5.13 current consumption in reset and reset pulsewidth figure 29-302. atmega3250a: reset supply current vs. v cc (0.1 - 1.0mhz, excluding current through the reset pull-up) 85 c 25 c -40 c 2 4 6 8 10 12 14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ma] 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre qu ency [mhz] i cc [ma] 489 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-303. atmega3250a: reset supply current vs. v cc (1 - 20mhz, excluding current through the reset pull-up) figure 29-304. atmega3250a: minimum reset pulse w idth vs. v cc 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.5 1 1.5 2 2.5 0 2 4 6 8 10 12 14 16 18 20 fre qu ency [mhz] i cc [ma] 85 c 25 c -40 c 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] p u l s ewidth [n s ] 490 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.6 atmega3250pa 29.6.1 active supply current figure 29-305. atmega3250pa: active supply current vs. frequency (0.1 - 1.0mhz) figure 29-306. atmega3250pa: active supply current vs. frequency (1 - 20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre qu ency [mhz] i cc [ma] 5.5 v 5.0 v 4.5 v 0 2 4 6 8 10 12 14 0 2 4 6 8 101214161820 fre qu ency [mhz] i cc [ma] 4.0 v 3.3 v 2.7 v 1.8 v 491 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-307. atmega3250pa: active supply current vs. v cc (internal rc o scillator, 8mhz figure 29-308. atmega3250pa: active supply current vs. v cc (internal rc o scillator, 1mhz) 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 492 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-309. atmega3250pa: active supply current vs. v cc (32khz w atch crystal) 29.6.2 idle supply current figure 29-310. atmega3250pa: idle supply current vs. frequency (0.1 - 1.0mhz) 85 c 25 c -40 c 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1.522.533.544.555.5 v cc [v] i cc [ma] 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency [mhz] i cc [ma] 493 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-311. atmega3250pa: idle supply current vs. frequency (1 - 20mhz) figure 29-312. atmega3250pa: idle supply current vs. v cc (internal rc o scillator, 8mhz) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0246 8 10 12 14 16 1 8 20 fre qu ency [mhz] i cc [ma] 4.0 v 4.5 v 2.7 v 3.3 v 1. 8 v 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 494 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-313. atmega3250pa: idle supply current vs. v cc (internal rc o scillator, 1 mhz) figure 29-314. atmega3250pa: idle supply current vs. v cc (32khz w atch crystal) 29.6.3 atmega3250pa : supply current of i/o modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 8 5 c 25 c -40 c 8 5 c 25 c -40 c 1 2 3 4 5 6 7 8 9 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [ v ] i cc [ma] 495 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 are controlled by the power reduction register. see ?power reduction register? on page 41 for details. it is possible to calculate the typical current consumption based on the numbers from table 29- 12 for other v cc and frequency settings than listed in table 29-11 . 29.6.3.1 example 1 calculate the expected current consumption in idle mode with usart0, timer1, and spi enabled at v cc = 3.0v and f = 1mhz. from table 29-11 , second column, we see that we need to add 13.1% for the usart0, 13.0% for the spi, and 13.2% for the timer1 module. reading from figure 29-311 , we find that the idle current consumption is ~0.09 ma at v cc = 3.0v and f = 1mhz. the total current consumption in idle mode with usart0, timer1, and spi enabled, gives: table 29-11. atmega3250pa: additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz pradc 7 a 44 a 195 a prusart0 6.9 a 43.5 a 210 a prspi 6.6 a 47 a 205 a prtim1 7 a 47 a 206 a table 29-12. atmega3250pa: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 29-305 and figure 29-306 ) additional current consumption compared to idle with external clock (see figure 29-310 and figure 29-311 ) pradc 3.2% 12.7% prusart0 3.4% 13.1% prspi 3.3% 13.0% prtim1 3.4% 13.2% i cc total 0.09 ma 1 0.131 0.13 0.132 +++ () ? 0.13 ma ? 496 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.6.4 power-down supply current figure 29-315. atmega3250pa: power-down supply current vs. v cc ( w atchdog timer disabled) figure 29-316. atmega3250pa: power-down supply current vs. v cc ( w atchdog timer enabled) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc [v] i cc [ u a] 85 c 25 c -40 c 2 4 6 8 10 12 14 16 18 20 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc [v] i cc [ u a] 497 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.6.5 power-save supply current figure 29-317. atmega3250pa: power-save supply current vs. v cc ( w atchdog timer disabled and 32khz crystal oscillator running) the differential current consumption between power-save with w d disabled and 32khz tosc represents the current drawn by timer/counter2. 29.6.6 standby supply current figure 29-318. atmega3250pa: standby supply current vs. v cc (32khz w atch crystal, w atch- dog timer disabled) 85 c 25 c -40 c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ma] 85 c 25 c -40 c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ma] 498 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-319. atmega3250pa: standby supply current vs. v cc (xtall and resonator, w atch- dog timer disabled) 29.6.7 pin pull-up figure 29-320. atmega3250pa: i/o pin pull-up resistor current vs. input voltage (v cc = 5v) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 1mhz_res 0.01 0.03 0.05 0.07 0.09 0.11 0.13 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 85 c 25 c -40 c 0 20 40 60 80 100 120 140 160 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v op [v] i op [ u a] 499 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-321. atmega3250pa: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) figure 29-322. atmega3250pa: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8v) 85 c 25 c -40 c 0 10 20 30 40 50 60 70 80 90 0 0.5 1 1.5 2 2.5 3 v op [v] i op [ u a] 85 c 25 c -40 c 0 10 20 30 40 50 60 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v op [v] i op [ u a] 500 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-323. atmega3250pa: reset pull-up resist or current vs. reset pin voltage (v cc = 5v) figure 29-324. atmega3250pa: reset pull-u p resistor current vs. reset pin voltage (v cc = 2.7v) 85 c 25 c -40 c 0 20 40 60 80 100 120 140 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset [v] i reset [ u a] 85 c 25 c -40 c 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 2.5 3 v reset [v] i reset [ u a] 501 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-325. atmega3250pa: reset pull-up resistor current vs. reset pin voltage (v cc = 1.8v) 29.6.8 pin driver strength figure 29-326. atmega3250pa: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =5v) 85 c 25 c -40 c 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v reset [v] i reset [ u a] 85 c 25 c -40 c 4.6 4.65 4.7 4.75 4.8 4.85 4.9 4.95 5 5.05 012345678910 i oh [ma] v oh [v] 502 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-327. atmega3250pa: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =2.7v) figure 29-328. atmega3250pa: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =1.8v) 85 c 25 c -40 c 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 012345678910 i oh [ma] v oh [v] 85 c 25 c -40 c 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 0 0.5 1 1.5 2 2.5 3 3.5 4 i oh [ma] v oh [v] 503 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-329. atmega3250pa: i/o pin output voltage vs. source current, port b (v cc = 5v) figure 29-330. atmega3250pa: i/o pin output volt age vs. source current, port b (v cc = 2.7v) 85c 25c -40c 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 5.1 0 2 4 6 8 10 12 14 16 18 20 i oh [ma] v oh [v] 85c 25c -40c 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 02468101214161820 i oh [ma] v oh [v] 504 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-331. atmega3250pa: i/o pin output volt age vs. source current, port b (v cc = 1.8v) figure 29-332. atmega3250pa: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 5v) 85c 25c -40c 1.3 1.4 1.5 1.6 1.7 1.8 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i oh [ma] v oh [v] 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 012345678910 i ol [ma] v ol [v] 505 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-333. atmega3250pa: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 2.7v) figure 29-334. atmega3250pa: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 1.8v) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 012345678910 i ol [ma] v ol [v] 85 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 i ol [ma] v ol [v] 506 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-335. atmega3250pa: i/o pin output voltage vs. sink current, port b (v cc = 5v) figure 29-336. atmega3250pa: i/o pin output voltage vs. sink current, port b (v cc = 2.7v) 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 02468101214161820 i ol [ma] v ol [v] 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 0 2 4 6 8 10 12 14 16 18 20 i ol [ma] v ol [v] 507 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-337. atmega3250pa: i/o pin output voltage vs. sink current, port b (v cc = 1.8v) 29.6.9 pin thresholds and hysteresis figure 29-338. atmega3250pa: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 85c 25c -40c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 i ol [ma] v ol [v] 8 5 c 25 c -40 c 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 508 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-339. atmega3250pa: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 29-340. atmega3250pa: i/o pin input hysteresis vs. v cc 8 5 c 25 c -40 c 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -40 c 0.25 0.29 0.33 0.37 0.41 0.45 0.49 0.53 0.57 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis (m v ) 509 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-341. atmega3250pa: reset input threshold voltage vs. v cc (v ih ,reset pin read as ?1?) figure 29-342. atmega3250pa: reset input threshold voltage vs. v cc (v il ,reset pin read as ?0?) 85 c 25 c -40 c 1 1.2 1.4 1.6 1.8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) thre s hold (v) 85 c 25 c -40 c 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) thre s hold (v) 510 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-343. atmega3250pa: reset input pin hysteresis vs. v cc 29.6.10 bod thresholds and analog comparator offset figure 29-344. atmega3250pa: bod thresholds vs. temperature (bod level is 4.3v) 8 5 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis (m v ) rising v cc falling v cc 4.225 4.25 4.275 4.3 4.325 4.35 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] bod threshold [ v ] 511 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-345. atmega3250pa: bod thresholds vs. temperature (bod level is 2.7v) figure 29-346. atmega3250pa: bod thresholds vs. temperature (bod level is 1.8v) rising v cc falling v cc 2.65 2.675 2.7 2.725 2.75 2.775 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] bod threshold [ v ] rising v cc falling v cc 1.7 8 5 1.795 1. 8 05 1. 8 15 1. 8 25 1. 8 35 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] bod threshold [ v ] 512 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-347. atmega3250pa: bandgap voltage vs. v cc figure 29-348. atmega3250pa: bandgap voltage vs. temperature 85 c 25 c -40 c 1.08 1.085 1.09 1.095 1.1 1.105 1.11 1.115 1.12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 vcc [v] b a ndg a p volt a ge [v] 5.5 v 4.0 v 2.7 v 1. 8 v 1.0 8 5 1.09 1.095 1.1 1.105 1.11 1.115 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re [c] bandgap v oltage [ v ] 513 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.6.11 internal oscillator speed figure 29-349. atmega3250pa: w atchdog oscillator frequency vs. v cc figure 29-350. atmega3250pa: w atchdog oscillator frequency vs. temperature 85c 25c -40c 1000 1025 1050 1075 1100 1125 1150 1175 1200 1225 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] f rc [khz] 5.5 v 5.0 v 4.5 v 4.0 v 3.0 v 2.7 v 1. 8 v 1000 1050 1100 1150 1200 1250 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 0 temperat u re [c] f rc [khz] 514 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-351. atmega3250pa: calib rated 8mhz rc oscillator fr equency vs. temperature figure 29-352. atmega3250pa: calibra ted 8mhz rc oscillator frequency vs. v cc 5.5 v 4.5 v 3.3 v 2.7 v 1. 8 v 7.4 7.5 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 8 .3 -40 -20 0 20 40 60 8 0 temperat u re [c] f rc [mhz] 85 c 25 c -40 c 7.4 7.5 7.6 7.7 7.8 7.9 8 8.1 8.2 8.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] f rc [mhz] 515 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-353. atmega3250pa: calib rated 8mhz rc oscillator fr equency vs. osccal value 29.6.12 current consumption of peripheral units figure 29-354. atmega3250pa: brownout detector current vs. v cc 0 2 4 6 8 10 12 14 16 016324 8 64 8 09611212 8 144 160 176 192 20 8 224 240 256 osccal [x1] f rc [mhz] -40 c 8 5 c 25 c 85 c 25 c -40 c 10 15 20 25 30 35 40 45 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 516 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-355. atmega3250pa: active supply cu rrent with adc at 50khz vs. v cc figure 29-356. atmega3250pa: active supply curr ent with adc at 200khz vs. v cc 85 c 25 c -40 c 150 175 200 225 250 275 300 325 350 375 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 85 c 25 c -40 c 125 150 175 200 225 250 275 300 325 350 375 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 517 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-357. atmega3250pa: active supply cu rrent with adc at 1mhz vs. v cc figure 29-358. atmega3250pa: aref external reference current vs. v cc 85 c 25 c -40 c 125 150 175 200 225 250 275 300 325 350 375 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 85 c 25 c -40 c 20 40 60 80 100 120 140 160 180 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 518 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-359. atmega3250pa: w atchdog timer current vs. v cc figure 29-360. atmega325a: analog comparator current vs. v cc 85 c 25 c -40 c 0 2.5 5 7.5 10 12.5 15 17.5 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 85 c 25 c -40 c 30 40 50 60 70 80 90 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ u a] 519 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-361. atmega3250pa: programming current vs. v cc 29.6.13 current consumption in reset and reset pulsewidth figure 29-362. atmega3250pa: reset su pply current vs. v cc (0.1 - 1.0mhz, excluding current through the reset pull-up) 85 c 25 c -40 c 2 4 6 8 10 12 14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] i cc [ma] 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre qu ency [mhz] i cc [ma] 520 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-363. atmega3250pa: reset su pply current vs. v cc (1 - 20mhz, excluding current through the reset pull-up) figure 29-364. atmega3250pa: minimum reset pulse w idth vs. v cc 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.5 1 1.5 2 2.5 0 2 4 6 8 10 12 14 16 18 20 fre qu ency [mhz] i cc [ma] 85 c 25 c -40 c 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc [v] p u l s ewidth [n s ] 521 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.7 atmega645a 29.7.1 active supply current figure 29-365. atmega645a: active supply current vs. low frequency (0.1 - 1.0mhz) figure 29-366. atmega645a: active supply current vs. frequency (1 - 20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.2 0.4 0.6 0.8 1 1.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 2 4 6 8 10 12 14 16 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 522 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-367. atmega645a: active supply current vs. v cc (internal rc oscillator, 8mhz) figure 29-368. atmega645a: active supply current vs. v cc (internal rc os cillator, 1mhz) 8 5 c 25 c -45 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 523 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-369. atmega645a: active supply current vs. v cc (32khz w atch crystal) 29.7.2 idle supply current figure 29-370. atmega645a: idle supply current vs.low frequency (0.1 - 1.0mhz) 8 5 c 25 c -45 c 8 12 16 20 24 2 8 32 36 40 1.522.533.544.555.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 524 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-371. atmega645a: idle supply current vs. frequency (1 - 20mhz) figure 29-372. atmega645a: idle supply current vs. v cc (internal rc oscillator, 8mhz) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 8 5 c 25 c -45 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 525 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-373. atmega645a: idle supply current vs. v cc (internal rc oscillator, 1mhz) figure 29-374. atmega645a: idle supply current vs. v cc (32khz w atch crystal) 29.7.3 atmega645a: supply current of i/o modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules 8 5 c 25 c -45 c 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8 .5 9.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 526 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 are controlled by the power reduction register. see ?prr ? power reduction register? on page 46 for details. it is possible to calculate the typical current consumption based on the numbers from table 29- 14 for other v cc and frequency settings than listed in table 29-13 . 29.7.3.1 example 1 calculate the expected current consumption in idle mode with usart0, timer1, and spi enabled at v cc = 3.0v and f = 1mhz. from table 29-14 , second column, we see that we need to add 49.8% for the usart0, 48.6% for the spi, and 46.3% for the timer1 module. reading from figure 29-371 , we find that the idle current consumption is ~0.13 ma at v cc = 3.0v and f = 1mhz. the total current consumption in idle mode with usart0, timer1, and spi enabled, gives: table 29-13. additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz pradc 23.75 a 212.1 a 938 a prusart0 36.7 a 210.4a 939 a prspi 32.1 a 213 a 940 a prtim1 24.2 a 217 a 940 a table 29-14. additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 29-365 and figure 29-366 ) additional current consumption compared to idle with external clock (see figure 29-370 and figure 29-371 ) pradc 11.9% 45.7% prusart0 13.2% 49.8% prspi 12.8% 48.6% prtim1 12.1% 46.3% i cc total 0.13 ma 1 0.498 0.486 0.463 +++ () ? 0.45 ma ? 527 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.7.4 power-down supply current figure 29-375. atmega645a: power-down supply current vs. v cc ( w atchdog timer disabled) figure 29-376. atmega645a: power-down supply current vs. v cc ( w atchdog timer enabled 8 5 c 25 c -45 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 2 4 6 8 10 12 14 16 1 8 20 1.522.533.544.555.5 v cc ( v ) i cc ( u a) 528 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-377. atmega645a: power-down supply current vs. v cc (32khz w atch crystal) 29.7.5 power-save supply current figure 29-378. atmega645a: power-save supply current vs. v cc ( w atchdog timer disabled and 32khz crystal oscillator running) the differential current consumption between power-save with w d disabled and 32khz tosc represents the current drawn by timer/counter2. 8 5 c 25 c -45 c 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 529 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.7.6 standby supply current figure 29-379. atmega645a: standby supply current vs. v cc (32khz w atch crystal, w atchdog timer disabled) figure 29-380. atmega645a: standby supply current vs. v cc (xtall and resonator, w atchdog timer disabled) 8 5 c 25 c -45 c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 1mhz_res 0.015 0.025 0.035 0.045 0.055 0.065 0.075 0.0 8 5 0.095 0.105 0.115 0.125 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 530 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.7.7 pin pull-up figure 29-381. atmega645a: i/o pin pull-up resistor current vs. input voltage (v cc = 5v) figure 29-382. atmega645a: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) 85 c 25 c -45 c 0 20 40 60 80 100 120 140 160 00.511.522.533.544.55 v op (v) i op ( u a) 85 c 25 c -45 c 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 3 v op (v) i op ( u a) 531 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-383. atmega645a: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8v) figure 29-384. atmega645a: reset pull-up resistor current vs. reset pin voltage (v cc = 5v) 85 c 25 c -45 c 0 5 10 15 20 25 30 35 40 45 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v op (v) i op ( u a) 8 5 c 25 c -45 c 0 15 30 45 60 75 90 105 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset ( v ) i reset ( u a) 532 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-385. atmega645a: reset pull-up resistor current vs. reset pin voltage (v cc = 2.7v) figure 29-386. atmega645a: reset pull-up resistor current vs. reset pin voltage (v cc = 1.8v) 8 5 c 25 c -45 c 0 6 12 1 8 24 30 36 42 4 8 54 60 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 v reset ( v ) i reset ( u a) 8 5 c 25 c -45 c 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v reset ( v ) i reset ( u a) 533 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.7.8 pin driver strength figure 29-387. atmega645a: i/o pin output voltage vs. sour ce current, ports a, c, d, e, f, g (v cc =5v) figure 29-388. atmega645a: i/o pin output voltage vs. sour ce current, ports a, c, d, e, f, g (v cc =2.7v) 8 5 c 25 c -45 c 4.55 4.6 4.65 4.7 4.75 4. 8 4. 8 5 4.9 4.95 5 01234567 8 910 i oh (ma) v oh ( v ) 8 5 c 25 c -45 c 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 01234567 8 910 i oh (ma) v oh ( v ) 534 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-389. atmega645a: i/o pin output voltage vs. sour ce current, ports a, c, d, e, f, g (v cc =1.8v) figure 29-390. atmega645a: i/o pin output voltage vs. source current, port b (v cc = 5v) 8 5 c 25 c -45 c 1.2 1.3 1.4 1.5 1.6 1.7 1. 8 0 0.5 1 1.5 2 2.5 3 3.5 4 i oh (ma) v oh ( v ) 8 5 c 25 c -45 c 4.3 4.4 4.5 4.6 4.7 4. 8 4.9 5 0246 8 10 12 14 16 1 8 20 i oh (ma) v oh ( v ) 535 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-391. atmega645a: i/o pin output voltage vs. source current, port b (v cc = 2.7v) figure 29-392. atmega645a: i/o pin output voltage vs. source current, port b (v cc = 1.8v) 8 5 c 25 c -45 c 1.2 1.4 1.6 1. 8 2 2.2 2.4 2.6 2. 8 0246 8 10 12 14 16 1 8 20 i oh (ma) v oh ( v ) 8 5 c 25 c -45 c 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1. 8 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i oh (ma) v oh ( v ) 536 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-393. atmega645a: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 5v) figure 29-394. atmega645a. i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 2.7v) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol ( v ) 8 5 c 25 c -45 c 0 0.2 0.4 0.6 0. 8 1 1.2 01234567 8 910 i ol (ma) v ol ( v ) 537 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-395. atmega645a: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 1.8v) figure 29-396. atmega645a: i/o pin output voltage vs. sink current, port b (v cc = 5v) 8 5 c 25 c -45 c 0 0.04 0.0 8 0.12 0.16 0.2 0.24 0.2 8 0.32 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 i ol (ma) v ol ( v ) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol ( v ) 538 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-397. atmega645a: i/o pin output voltage vs. sink current, port b (v cc = 2.7v9 figure 29-398. atmega645a: i/o pin output voltage vs. sink current, port b (v cc = 1.8v) 8 5 c 25 c -45 c 0 0.2 0.4 0.6 0. 8 1 1.2 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol ( v ) 8 5 c 25 c -45 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 i ol (ma) v ol ( v ) 539 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.7.9 pin threshold and hysteresis figure 29-399. atmega645a: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 29-400. atmega645a: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0? 8 5 c 25 c -45 c 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -45 c 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 540 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-401. atmega645a: i/o pin input hysteresis vs. v cc figure 29-402. atmega645a: reset input threshold voltage vs. v cc ( v ih ,reset pin read as ?1? ) 8 5 c 25 c -45 c 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis ( v ) -45 c 8 5 c 25 c -45 c 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 541 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-403. atmega645a: reset input threshold voltage vs. v cc (v il ,reset pin read as ?0?) figure 29-404. atmega645a: reset input pin hysteresis vs. v cc 8 5 c 25 c -45 c 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis (m v ) 542 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.7.10 bod thresholds and analog comparator offset figure 29-405. atmega645a: bod thresholds vs. temperature (bod level is 4.3v) figure 29-406. atmega645a: bod thresholds vs. temperature (bod level is 2.7v) rising v cc falling v cc 4.29 4.31 4.33 4.35 4.37 4.39 4.41 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) rising v cc falling v cc 2.6 8 5 2.695 2.705 2.715 2.725 2.735 2.745 2.755 2.765 2.775 2.7 8 5 2.795 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) 543 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-407. atmega645a: bod thresholds vs. temperature (bod level is 1.8v) figure 29-408. atmega645a: bandgap voltage vs. v cc rising v cc falling v cc 1. 8 1. 8 05 1. 8 1 1. 8 15 1. 8 2 1. 8 25 1. 8 3 1. 8 35 1. 8 4 1. 8 45 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) 8 5 c 25 c -45 c 1.0 8 3 1.0 8 5 1.0 8 7 1.0 8 9 1.091 1.093 1.095 1.097 1.099 1.101 1.103 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) bandgap v oltage ( v ) 544 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-409. atmega645a: bandgap voltage vs. temperature 29.7.11 internal oscillator speed figure 29-410. atmega645a: w atchdog oscillator frequency vs. v cc 1.092 1.094 1.096 1.09 8 1.1 1.102 1.104 1.106 1.10 8 1.11 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bandgap v oltage ( v ) 1. 8 v 5.5 v 5.0 v 3.3 v 8 5 c 25 c -45 c 1050 10 8 0 1110 1140 1170 1200 1230 1260 1290 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) f rc (khz) 545 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-411. atmega645a: w atchdog oscillator frequ ency vs. temperature figure 29-412. atmega645a: calibrated 8m hz rc oscillator freq uency vs. temperature 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 1050 10 8 0 1110 1140 1170 1200 1230 1260 1290 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) f rc (khz) 5.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 7.3 7.4 7.5 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) f rc (mhz) 546 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-413. atmega645a: calibrate d 8mhz rc oscillato r frequency vs. v cc figure 29-414. atmega645a: calibrated 8m hz rc oscillator freq uency vs. osccal value 8 5 c 25 c -45 c 7.3 7.4 7.5 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) f rc (mhz) 8 5 c 25 c -45 c 2 4 6 8 10 12 14 16 1 8 016324 8 64 8 09611212 8 144 160 176 192 20 8 224 240 256 osccal (x1) f rc (mhz) 547 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.7.12 current consumption of peripheral units figure 29-415. atmega645a: brownout detector current vs. v cc figure 29-416. atmega645a: active supply current with adc at 50khz vs. v cc 8 5 c 25 c -45 c 12 15 1 8 21 24 27 30 33 36 39 42 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 120 150 1 8 0 210 240 270 300 330 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 548 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-417. atmega645a: active supply current with adc at 200khz vs. v cc figure 29-418. atmega645a: active supply current with adc at 1mhz vs. v cc 8 5 c 25 c -45 c 120 150 1 8 0 210 240 270 300 330 360 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 130 160 190 220 250 2 8 0 310 340 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 549 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-419. atmega645a: aref external reference current vs. v cc figure 29-420. atmega645a: w atchdog timer current vs. v cc 8 5 c 25 c -45 c 50 65 8 0 95 110 125 140 155 170 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 2 4 6 8 10 12 14 16 1 8 1.522.533.544.555.5 v cc ( v ) i cc ( u a) 550 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-421. atmega645a: analog comparator current vs. v cc figure 29-422. atmega645a: programming current vs. v cc 8 5 c 25 c -45 c 30 40 50 60 70 8 0 90 100 110 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 2 4 6 8 10 12 14 16 1 8 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 551 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.7.13 current consumption in reset and reset pulswidth figure 29-423. atmega645a: reset supply current vs. v cc (0.1 - 1.0mhz, excluding current through the reset pull-up figure 29-424. atmega645a: reset supply current vs. v cc (1 - 16mhz, excluding current through the reset pull-up) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 552 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-425. atmega645a: minimum reset pulse w idth vs. v cc 8 5 c 25 c -45 c 0 300 600 900 1200 1500 1 8 00 2100 2400 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) p u lse w idth (ns) 553 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.8 atmega645p 29.8.1 active supply current figure 29-426. atmega645p: active supply current vs. low frequency (0.1 - 1.0mhz) figure 29-427. atmega645p: active supply current vs. frequency (1 - 20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.2 0.4 0.6 0.8 1 1.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 2 4 6 8 10 12 14 16 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 554 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-428. atmega645p: active supply current vs. v cc (internal rc oscillator, 8mhz) figure 29-429. atmega645p: active supply current vs. v cc (internal rc os cillator, 1mhz) 8 5 c 25 c -45 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 555 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-430. atmega645p: active supply current vs. v cc (32khz w atch crystal) 29.8.2 idle supply current figure 29-431. atmega645p: idle supply current vs.low frequency (0.1 - 1.0mhz) 8 5 c 25 c -45 c 8 12 16 20 24 2 8 32 36 40 1.522.533.544.555.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 556 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-432. atmega645p: idle supply current vs. frequency (1 - 20mhz) figure 29-433. atmega645p: idle supply current vs. v cc (internal rc oscillator, 8mhz) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 8 5 c 25 c -45 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 557 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-434. atmega645p: idle supply current vs. v cc (internal rc oscillator, 1mhz) figure 29-435. atmega645p: idle supply current vs. v cc (32khz w atch crystal) 29.8.3 atmega645p: supply current of i/o modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules 8 5 c 25 c -45 c 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8 .5 9.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 558 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 are controlled by the power reduction register. see ?prr ? power reduction register? on page 46 for details. it is possible to calculate the typical current consumption based on the numbers from table 29- 14 for other v cc and frequency settings than listed in table 29-13 . 29.8.3.1 example 1 calculate the expected current consumption in idle mode with usart0, timer1, and spi enabled at v cc = 3.0v and f = 1mhz. from table 29-14 , second column, we see that we need to add 49.8% for the usart0, 48.6% for the spi, and 46.3% for the timer1 module. reading from figure 29-371 , we find that the idle current consumption is ~0.13 ma at v cc = 3.0v and f = 1mhz. the total current consumption in idle mode with usart0, timer1, and spi enabled, gives: table 29-15. additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz pradc 23.75 a 212.1 a 938 a prusart0 36.7 a 210.4a 939 a prspi 32.1 a 213 a 940 a prtim1 24.2 a 217 a 940 a table 29-16. additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 29-365 and figure 29-366 ) additional current consumption compared to idle with external clock (see figure 29-370 and figure 29-371 ) pradc 11.9% 45.7% prusart0 13.2% 49.8% prspi 12.8% 48.6% prtim1 12.1% 46.3% i cc total 0.13 ma 1 0.498 0.486 0.463 +++ () ? 0.45 ma ? 559 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.8.4 power-down supply current figure 29-436. atmega645p: power-down supply current vs. v cc ( w atchdog timer disabled) figure 29-437. atmega645p: power-down supply current vs. v cc ( w atchdog timer enabled 8 5 c 25 c -45 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 2 4 6 8 10 12 14 16 1 8 20 1.522.533.544.555.5 v cc ( v ) i cc ( u a) 560 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-438. atmega645p: power-down supply current vs. v cc (32khz w atch crystal) 29.8.5 power-save supply current figure 29-439. atmega645p: power-save supply current vs. v cc ( w atchdog timer disabled and 32khz crystal oscillator running) the differential current consumption between power-save with w d disabled and 32khz tosc represents the current drawn by timer/counter2. 8 5 c 25 c -45 c 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 561 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.8.6 standby supply current figure 29-440. atmega645p: standby supply current vs. v cc (32khz w atch crystal, w atchdog timer disabled) figure 29-441. atmega645p: standby supply current vs. v cc (xtall and resonator, w atchdog timer disabled) 8 5 c 25 c -45 c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 1mhz_res 0.015 0.025 0.035 0.045 0.055 0.065 0.075 0.0 8 5 0.095 0.105 0.115 0.125 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 562 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.8.7 pin pull-up figure 29-442. atmega645p: i/o pin pull-up resistor current vs. input voltage (v cc = 5v) figure 29-443. atmega645p: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) 85 c 25 c -45 c 0 20 40 60 80 100 120 140 160 00.511.522.533.544.55 v op (v) i op ( u a) 85 c 25 c -45 c 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 3 v op (v) i op ( u a) 563 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-444. atmega645p: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8v) figure 29-445. atmega645p: reset pull-up resistor current vs. reset pin voltage (v cc = 5v) 85 c 25 c -45 c 0 5 10 15 20 25 30 35 40 45 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v op (v) i op ( u a) 8 5 c 25 c -45 c 0 15 30 45 60 75 90 105 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset ( v ) i reset ( u a) 564 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-446. atmega645p: reset pull-up resistor current vs. reset pin voltage (v cc = 2.7v) figure 29-447. atmega645p: reset pull-up resistor current vs. reset pin voltage (v cc = 1.8v) 8 5 c 25 c -45 c 0 6 12 1 8 24 30 36 42 4 8 54 60 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 v reset ( v ) i reset ( u a) 8 5 c 25 c -45 c 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v reset ( v ) i reset ( u a) 565 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.8.8 pin driver strength figure 29-448. atmega645p: i/o pin output voltage vs. sour ce current, ports a, c, d, e, f, g (v cc =5v) figure 29-449. atmega645p: i/o pin output voltage vs. sour ce current, ports a, c, d, e, f, g (v cc =2.7v) 8 5 c 25 c -45 c 4.55 4.6 4.65 4.7 4.75 4. 8 4. 8 5 4.9 4.95 5 01234567 8 910 i oh (ma) v oh ( v ) 8 5 c 25 c -45 c 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 01234567 8 910 i oh (ma) v oh ( v ) 566 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-450. atmega645p: i/o pin output voltage vs. sour ce current, ports a, c, d, e, f, g (v cc =1.8v) figure 29-451. atmega645a: i/o pin output voltage vs. source current, port b (v cc = 5v) 8 5 c 25 c -45 c 1.2 1.3 1.4 1.5 1.6 1.7 1. 8 0 0.5 1 1.5 2 2.5 3 3.5 4 i oh (ma) v oh ( v ) 8 5 c 25 c -45 c 4.3 4.4 4.5 4.6 4.7 4. 8 4.9 5 0246 8 10 12 14 16 1 8 20 i oh (ma) v oh ( v ) 567 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-452. atmega645p: i/o pin output voltage vs. source current, port b (v cc = 2.7v) figure 29-453. atmega645p: i/o pin output voltage vs. source current, port b (v cc = 1.8v) 8 5 c 25 c -45 c 1.2 1.4 1.6 1. 8 2 2.2 2.4 2.6 2. 8 0246 8 10 12 14 16 1 8 20 i oh (ma) v oh ( v ) 8 5 c 25 c -45 c 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1. 8 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i oh (ma) v oh ( v ) 568 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-454. atmega645p: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 5v) figure 29-455. atmega645p: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 2.7v) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol ( v ) 8 5 c 25 c -45 c 0 0.2 0.4 0.6 0. 8 1 1.2 01234567 8 910 i ol (ma) v ol ( v ) 569 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-456. atmega645p: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 1.8v) figure 29-457. atmega645p: i/o pin output voltage vs. sink current, port b (v cc = 5v) 8 5 c 25 c -45 c 0 0.04 0.0 8 0.12 0.16 0.2 0.24 0.2 8 0.32 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 i ol (ma) v ol ( v ) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol ( v ) 570 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-458. atmega645p: i/o pin output voltage vs. sink current, port b (v cc = 2.7v9 figure 29-459. atmega645p: i/o pin output voltage vs. sink current, port b (v cc = 1.8v) 8 5 c 25 c -45 c 0 0.2 0.4 0.6 0. 8 1 1.2 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol ( v ) 8 5 c 25 c -45 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 i ol (ma) v ol ( v ) 571 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.8.9 pin threshold and hysteresis figure 29-460. atmega645p: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 29-461. atmega645p: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0? 8 5 c 25 c -45 c 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -45 c 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 572 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-462. atmega645p: i/o pin input hysteresis vs. v cc figure 29-463. atmega645p: reset input threshold voltage vs. v cc ( v ih ,reset pin read as ?1? ) 8 5 c 25 c -45 c 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis ( v ) -45 c 8 5 c 25 c -45 c 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 573 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-464. atmega645p: reset input threshold voltage vs. v cc (v il ,reset pin read as ?0?) figure 29-465. atmega645p: reset input pin hysteresis vs. v cc 8 5 c 25 c -45 c 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis (m v ) 574 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.8.10 bod thresholds and analog comparator offset figure 29-466. atmega645p: bod thresholds vs. temperature (bod level is 4.3v) figure 29-467. atmega645p: bod thresholds vs. temperature (bod level is 2.7v) rising v cc falling v cc 4.29 4.31 4.33 4.35 4.37 4.39 4.41 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) rising v cc falling v cc 2.6 8 5 2.695 2.705 2.715 2.725 2.735 2.745 2.755 2.765 2.775 2.7 8 5 2.795 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) 575 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-468. atmega645p: bod thresholds vs. temperature (bod level is 1.8v) figure 29-469. atmega645p: bandgap voltage vs. v cc rising v cc falling v cc 1. 8 1. 8 05 1. 8 1 1. 8 15 1. 8 2 1. 8 25 1. 8 3 1. 8 35 1. 8 4 1. 8 45 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) 8 5 c 25 c -45 c 1.0 8 3 1.0 8 5 1.0 8 7 1.0 8 9 1.091 1.093 1.095 1.097 1.099 1.101 1.103 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) bandgap v oltage ( v ) 576 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-470. atmega645p: bandgap voltage vs. temperature 29.8.11 internal oscillator speed figure 29-471. atmega645p: w atchdog oscillator frequency vs. v cc 1.092 1.094 1.096 1.09 8 1.1 1.102 1.104 1.106 1.10 8 1.11 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bandgap v oltage ( v ) 1. 8 v 5.5 v 5.0 v 3.3 v 8 5 c 25 c -45 c 1050 10 8 0 1110 1140 1170 1200 1230 1260 1290 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) f rc (khz) 577 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-472. atmega645p: w atchdog oscillator frequ ency vs. temperature figure 29-473. atmega645p: calibrated 8m hz rc oscillator freq uency vs. temperature 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 1050 10 8 0 1110 1140 1170 1200 1230 1260 1290 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) f rc (khz) 5.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 7.3 7.4 7.5 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) f rc (mhz) 578 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-474. atmega645p: calibrate d 8mhz rc oscillato r frequency vs. v cc figure 29-475. atmega645p: calibrated 8m hz rc oscillator freq uency vs. osccal value 8 5 c 25 c -45 c 7.3 7.4 7.5 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) f rc (mhz) 8 5 c 25 c -45 c 2 4 6 8 10 12 14 16 1 8 016324 8 64 8 09611212 8 144 160 176 192 20 8 224 240 256 osccal (x1) f rc (mhz) 579 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.8.12 current consumption of peripheral units figure 29-476. atmega645p: brownout detector current vs. v cc figure 29-477. atmega645p: active supply current with adc at 50khz vs. v cc 8 5 c 25 c -45 c 12 15 1 8 21 24 27 30 33 36 39 42 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 120 150 1 8 0 210 240 270 300 330 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 580 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-478. atmega645p: active supply current with adc at 200khz vs. v cc figure 29-479. atmega645p: active supply current with adc at 1mhz vs. v cc 8 5 c 25 c -45 c 120 150 1 8 0 210 240 270 300 330 360 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 130 160 190 220 250 2 8 0 310 340 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 581 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-480. atmega645p: aref external reference current vs. v cc figure 29-481. atmega645p: w atchdog timer current vs. v cc 8 5 c 25 c -45 c 50 65 8 0 95 110 125 140 155 170 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 2 4 6 8 10 12 14 16 1 8 1.522.533.544.555.5 v cc ( v ) i cc ( u a) 582 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-482. atmega645p: analog comparator current vs. v cc figure 29-483. atmega645p: programming current vs. v cc 8 5 c 25 c -45 c 30 40 50 60 70 8 0 90 100 110 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 2 4 6 8 10 12 14 16 1 8 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 583 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.8.13 current consumption in reset and reset pulswidth figure 29-484. atmega645p: reset supply current vs. v cc (0.1 - 1.0mhz, excluding current through the reset pull-up figure 29-485. atmega645p: reset supply current vs. v cc (1 - 16mhz, excluding current through the reset pull-up) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 584 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-486. atmega645p: minimum reset pulse w idth vs. v cc 8 5 c 25 c -45 c 0 300 600 900 1200 1500 1 8 00 2100 2400 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) p u lse w idth (ns) 585 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.9 atmega6490a 29.9.1 active supply current figure 29-487. atmega6450a: active supply current vs. low frequency (0.1 - 1.0mhz) figure 29-488. atmega6450a: active supply current vs. frequency (1 - 20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.2 0.4 0.6 0.8 1 1.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 2 4 6 8 10 12 14 16 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 586 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-489. atmega6450a: active supply current vs. v cc (internal rc o scillator, 8mhz) figure 29-490. atmega6450a: active supply current vs. v cc (internal rc o scillator, 1mhz) 8 5 c 25 c -45 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 587 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-491. atmega6450a: active supply current vs. v cc (32khz w atch crystal) 29.9.2 idle supply current figure 29-492. atmega6450a: idle supply current vs.low frequency (0.1 - 1.0mhz) 8 5 c 25 c -45 c 8 12 16 20 24 2 8 32 36 40 1.522.533.544.555.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 588 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-493. atmega6450a: idle supply current vs. frequency (1 - 20mhz) figure 29-494. atmega6450a: idle su pply current vs. v cc (internal rc o scillator, 8mhz) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 8 5 c 25 c -45 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 589 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-495. atmega6450a: idle su pply current vs. v cc (internal rc o scillator, 1mhz) figure 29-496. atmega6450a: idle su pply current vs. v cc (32khz w atch crystal) 29.9.3 atmega6450a: supply current of i/o modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules 8 5 c 25 c -45 c 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8 .5 9.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 590 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 are controlled by the power reduction register. see ?prr ? power reduction register? on page 46 for details. it is possible to calculate the typical current consumption based on the numbers from table 29- 14 for other v cc and frequency settings than listed in table 29-13 . 29.9.3.1 example 1 calculate the expected current consumption in idle mode with usart0, timer1, and spi enabled at v cc = 3.0v and f = 1mhz. from table 29-14 , second column, we see that we need to add 49.8% for the usart0, 48.6% for the spi, and 46.3% for the timer1 module. reading from figure 29-371 , we find that the idle current consumption is ~0.13 ma at v cc = 3.0v and f = 1mhz. the total current consumption in idle mode with usart0, timer1, and spi enabled, gives: table 29-17. additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz pradc 23.75 a 212.1 a 938 a prusart0 36.7 a 210.4a 939 a prspi 32.1 a 213 a 940 a prtim1 24.2 a 217 a 940 a table 29-18. additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 29-365 and figure 29-366 ) additional current consumption compared to idle with external clock (see figure 29-370 and figure 29-371 ) pradc 11.9% 45.7% prusart0 13.2% 49.8% prspi 12.8% 48.6% prtim1 12.1% 46.3% i cc total 0.13 ma 1 0.498 0.486 0.463 +++ () ? 0.45 ma ? 591 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.9.4 power-down supply current figure 29-497. atmega6450a: power-down supply current vs. v cc ( w atchdog timer disabled) figure 29-498. atmega6450a: power-down supply current vs. v cc ( w atchdog timer enabled 8 5 c 25 c -45 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 2 4 6 8 10 12 14 16 1 8 20 1.522.533.544.555.5 v cc ( v ) i cc ( u a) 592 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-499. atmega6450a: power-down supply current vs. v cc (32khz w atch crystal) 29.9.5 power-save supply current figure 29-500. atmega6450a: power-save supply current vs. v cc ( w atchdog timer disabled and 32khz crystal oscillator running) the differential current consumption between power-save with w d disabled and 32khz tosc represents the current drawn by timer/counter2. 8 5 c 25 c -45 c 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 593 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.9.6 standby supply current figure 29-501. atmega6450a: standby supply current vs. v cc (32khz w atch crystal, w atch- dog timer disabled) figure 29-502. atmega6450a: standby supply current vs. v cc (xtall and resonator, w atchdog timer disabled) 8 5 c 25 c -45 c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 1mhz_res 0.015 0.025 0.035 0.045 0.055 0.065 0.075 0.0 8 5 0.095 0.105 0.115 0.125 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 594 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.9.7 pin pull-up figure 29-503. atmega6450a: i/o pin pull-up resistor current vs. input voltage (v cc = 5v) figure 29-504. atmega6450a: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) 85 c 25 c -45 c 0 20 40 60 80 100 120 140 160 00.511.522.533.544.55 v op (v) i op ( u a) 85 c 25 c -45 c 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 3 v op (v) i op ( u a) 595 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-505. atmega6450a: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8v) figure 29-506. atmega6450a: reset pull-up resistor current vs. reset pin voltage (v cc = 5v) 85 c 25 c -45 c 0 5 10 15 20 25 30 35 40 45 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v op (v) i op ( u a) 8 5 c 25 c -45 c 0 15 30 45 60 75 90 105 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset ( v ) i reset ( u a) 596 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-507. atmega6450a: reset pull-up resistor current vs. reset pin voltage (v cc = 2.7v) figure 29-508. atmega6450a: reset pull-up resistor current vs. reset pin voltage (v cc = 1.8v) 8 5 c 25 c -45 c 0 6 12 1 8 24 30 36 42 4 8 54 60 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 v reset ( v ) i reset ( u a) 8 5 c 25 c -45 c 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v reset ( v ) i reset ( u a) 597 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.9.8 pin driver strength figure 29-509. atmega6450a: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =5v) figure 29-510. atmega6450a: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =2.7v) 8 5 c 25 c -45 c 4.55 4.6 4.65 4.7 4.75 4. 8 4. 8 5 4.9 4.95 5 01234567 8 910 i oh (ma) v oh ( v ) 8 5 c 25 c -45 c 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 01234567 8 910 i oh (ma) v oh ( v ) 598 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-511. atmega6450a: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =1.8v) figure 29-512. atmega6450a: i/o pin output voltage vs. source current, port b (v cc = 5v) 8 5 c 25 c -45 c 1.2 1.3 1.4 1.5 1.6 1.7 1. 8 0 0.5 1 1.5 2 2.5 3 3.5 4 i oh (ma) v oh ( v ) 8 5 c 25 c -45 c 4.3 4.4 4.5 4.6 4.7 4. 8 4.9 5 0246 8 10 12 14 16 1 8 20 i oh (ma) v oh ( v ) 599 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-513. atmega6450a: i/o pin output voltage vs. source current, port b (v cc = 2.7v) figure 29-514. atmega6450a: i/o pin output voltage vs. source current, port b (v cc = 1.8v) 8 5 c 25 c -45 c 1.2 1.4 1.6 1. 8 2 2.2 2.4 2.6 2. 8 0246 8 10 12 14 16 1 8 20 i oh (ma) v oh ( v ) 8 5 c 25 c -45 c 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1. 8 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i oh (ma) v oh ( v ) 600 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-515. atmega6450a: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 5v) figure 29-516. atmega6450a: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 2.7v) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol ( v ) 8 5 c 25 c -45 c 0 0.2 0.4 0.6 0. 8 1 1.2 01234567 8 910 i ol (ma) v ol ( v ) 601 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-517. atmega6450a: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 1.8v) figure 29-518. atmega6450a: i/o pin output voltage vs. sink current, port b (v cc = 5v) 8 5 c 25 c -45 c 0 0.04 0.0 8 0.12 0.16 0.2 0.24 0.2 8 0.32 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 i ol (ma) v ol ( v ) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol ( v ) 602 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-519. atmega6450a: i/o pin output voltage vs. sink current, port b (v cc = 2.7v9 figure 29-520. atmega6450a: i/o pin output voltage vs. sink current, port b (v cc = 1.8v) 8 5 c 25 c -45 c 0 0.2 0.4 0.6 0. 8 1 1.2 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol ( v ) 8 5 c 25 c -45 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 i ol (ma) v ol ( v ) 603 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.9.9 pin threshold and hysteresis figure 29-521. atmega6450a: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 29-522. atmega6450a: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0? 8 5 c 25 c -45 c 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -45 c 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 604 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-523. atmega6450a: i/o pin input hysteresis vs. v cc figure 29-524. atmega6450a: reset input threshold voltage vs. v cc ( v ih ,reset pin read as ?1? ) 8 5 c 25 c -45 c 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis ( v ) -45 c 8 5 c 25 c -45 c 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 605 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-525. atmega6450a: reset input threshold voltage vs. v cc (v il ,reset pin read as ?0?) figure 29-526. atmega6450a: reset input pin hysteresis vs. v cc 8 5 c 25 c -45 c 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis (m v ) 606 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.9.10 bod thresholds and analog comparator offset figure 29-527. atmega6450a: bod thresholds vs. temperature (bod level is 4.3v) figure 29-528. atmega6450a: bod thresholds vs. temperature (bod level is 2.7v) rising v cc falling v cc 4.29 4.31 4.33 4.35 4.37 4.39 4.41 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) rising v cc falling v cc 2.6 8 5 2.695 2.705 2.715 2.725 2.735 2.745 2.755 2.765 2.775 2.7 8 5 2.795 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) 607 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-529. atmega6450a: bod thresholds vs. temperature (bod level is 1.8v) figure 29-530. atmega6450a: bandgap voltage vs. v cc rising v cc falling v cc 1. 8 1. 8 05 1. 8 1 1. 8 15 1. 8 2 1. 8 25 1. 8 3 1. 8 35 1. 8 4 1. 8 45 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) 8 5 c 25 c -45 c 1.0 8 3 1.0 8 5 1.0 8 7 1.0 8 9 1.091 1.093 1.095 1.097 1.099 1.101 1.103 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) bandgap v oltage ( v ) 608 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-531. atmega6450a: bandgap voltage vs. temperature 29.9.11 internal oscillator speed figure 29-532. atmega6450a: w atchdog oscillator frequency vs. v cc 1.092 1.094 1.096 1.09 8 1.1 1.102 1.104 1.106 1.10 8 1.11 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bandgap v oltage ( v ) 1. 8 v 5.5 v 5.0 v 3.3 v 8 5 c 25 c -45 c 1050 10 8 0 1110 1140 1170 1200 1230 1260 1290 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) f rc (khz) 609 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-533. atmega6450a: w atchdog oscillator freq uency vs. temperature figure 29-534. atmega6450a: calibrated 8mhz rc os cillator frequency vs. temperature 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 1050 10 8 0 1110 1140 1170 1200 1230 1260 1290 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) f rc (khz) 5.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 7.3 7.4 7.5 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) f rc (mhz) 610 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-535. atmega6450a: calibrated 8mhz rc oscillator frequency vs. v cc figure 29-536. atmega6450a: calibrated 8mhz rc osc illator frequency vs. osccal value 8 5 c 25 c -45 c 7.3 7.4 7.5 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) f rc (mhz) 8 5 c 25 c -45 c 2 4 6 8 10 12 14 16 1 8 016324 8 64 8 09611212 8 144 160 176 192 20 8 224 240 256 osccal (x1) f rc (mhz) 611 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.9.12 current consumption of peripheral units figure 29-537. atmega6450a: brownout detector current vs. v cc figure 29-538. atmega6450a: active supply current with adc at 50khz vs. v cc 8 5 c 25 c -45 c 12 15 1 8 21 24 27 30 33 36 39 42 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 120 150 1 8 0 210 240 270 300 330 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 612 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-539. atmega645p: active supply current with adc at 200khz vs. v cc figure 29-540. atmega6450a: active supply current with adc at 1mhz vs. v cc 8 5 c 25 c -45 c 120 150 1 8 0 210 240 270 300 330 360 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 130 160 190 220 250 2 8 0 310 340 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 613 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-541. atmega6450a: aref external reference current vs. v cc figure 29-542. atmega6450a: w atchdog timer current vs. v cc 8 5 c 25 c -45 c 50 65 8 0 95 110 125 140 155 170 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 2 4 6 8 10 12 14 16 1 8 1.522.533.544.555.5 v cc ( v ) i cc ( u a) 614 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-543. atmega6450a: analog comparator current vs. v cc figure 29-544. atmega6450a: programming current vs. v cc 8 5 c 25 c -45 c 30 40 50 60 70 8 0 90 100 110 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 2 4 6 8 10 12 14 16 1 8 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 615 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.9.13 current consumption in reset and reset pulswidth figure 29-545. atmega6450a: reset supply current vs. v cc (0.1 - 1.0mhz, excluding current through the reset pull-up figure 29-546. atmega6450a: reset supply current vs. v cc (1 - 16mhz, excluding current through the reset pull-up) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 616 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-547. atmega6450a: minimum reset pulse w idth vs. v cc 8 5 c 25 c -45 c 0 300 600 900 1200 1500 1 8 00 2100 2400 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) p u lse w idth (ns) 617 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.10 atmega6450p 29.10.1 active supply current figure 29-548. atmega6450a: active supply current vs. low frequency (0.1 - 1.0mhz) figure 29-549. atmega6450a: active supply current vs. frequency (1 - 20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.2 0.4 0.6 0.8 1 1.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 2 4 6 8 10 12 14 16 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 618 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-550. atmega6450a: active supply current vs. v cc (internal rc o scillator, 8mhz) figure 29-551. atmega6450a: active supply current vs. v cc (internal rc o scillator, 1mhz) 8 5 c 25 c -45 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 619 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-552. atmega6450a: active supply current vs. v cc (32khz w atch crystal) 29.10.2 idle supply current figure 29-553. atmega6450a: idle supply current vs. low frequency (0.1 - 1.0mhz) 8 5 c 25 c -45 c 8 12 16 20 24 2 8 32 36 40 1.522.533.544.555.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 620 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-554. atmega6450a: idle supply current vs. frequency (1 - 20mhz) figure 29-555. atmega6450a: idle su pply current vs. v cc (internal rc o scillator, 8mhz) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 8 5 c 25 c -45 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 621 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-556. atmega6450a: idle su pply current vs. v cc (internal rc o scillator, 1mhz) figure 29-557. atmega6450a: idle su pply current vs. v cc (32khz w atch crystal) 29.10.3 atmega6450a: supply current of i/o modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules 8 5 c 25 c -45 c 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8 .5 9.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 622 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 are controlled by the power reduction register. see ?prr ? power reduction register? on page 46 for details. it is possible to calculate the typical current consumption based on the numbers from table 29- 14 for other v cc and frequency settings than listed in table 29-13 . 29.10.3.1 example 1 calculate the expected current consumption in idle mode with usart0, timer1, and spi enabled at v cc = 3.0v and f = 1mhz. from table 29-14 , second column, we see that we need to add 49.8% for the usart0, 48.6% for the spi, and 46.3% for the timer1 module. reading from figure 29-371 , we find that the idle current consumption is ~0.13 ma at v cc = 3.0v and f = 1mhz. the total current consumption in idle mode with usart0, timer1, and spi enabled, gives: table 29-19. additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz pradc 23.75 a 212.1 a 938 a prusart0 36.7 a 210.4a 939 a prspi 32.1 a 213 a 940 a prtim1 24.2 a 217 a 940 a table 29-20. additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 29-365 and figure 29-366 ) additional current consumption compared to idle with external clock (see figure 29-370 and figure 29-371 ) pradc 11.9% 45.7% prusart0 13.2% 49.8% prspi 12.8% 48.6% prtim1 12.1% 46.3% i cc total 0.13 ma 1 0.498 0.486 0.463 +++ () ? 0.45 ma ? 623 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.10.4 power-down supply current figure 29-558. atmega6450a: power-down supply current vs. v cc ( w atchdog timer disabled) figure 29-559. atmega6450a: power-down supply current vs. v cc ( w atchdog timer enabled 8 5 c 25 c -45 c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 2 4 6 8 10 12 14 16 1 8 20 1.522.533.544.555.5 v cc ( v ) i cc ( u a) 624 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-560. atmega6450a: power-down supply current vs. v cc (32khz w atch crystal) 29.10.5 power-save supply current figure 29-561. atmega6450a: power-save supply current vs. v cc ( w atchdog timer disabled and 32khz crystal oscillator running) the differential current consumption between power-save with w d disabled and 32khz tosc represents the current drawn by timer/counter2. 8 5 c 25 c -45 c 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -45 c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 625 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.10.6 standby supply current figure 29-562. atmega6450a: standby supply current vs. v cc (32khz w atch crystal, w atch- dog timer disabled) figure 29-563. atmega6450a: standby supply current vs. v cc (xtall and resonator, w atchdog timer disabled) 8 5 c 25 c -45 c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 1mhz_res 0.015 0.025 0.035 0.045 0.055 0.065 0.075 0.0 8 5 0.095 0.105 0.115 0.125 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 626 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.10.7 pin pull-up figure 29-564. atmega6450a: i/o pin pull-up resistor current vs. input voltage (v cc = 5v) figure 29-565. atmega6450a: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) 85 c 25 c -45 c 0 20 40 60 80 100 120 140 160 00.511.522.533.544.55 v op (v) i op ( u a) 85 c 25 c -45 c 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 3 v op (v) i op ( u a) 627 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-566. atmega6450a: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8v) figure 29-567. atmega6450a: reset pull-up resistor current vs. reset pin voltage (v cc = 5v) 85 c 25 c -45 c 0 5 10 15 20 25 30 35 40 45 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v op (v) i op ( u a) 8 5 c 25 c -45 c 0 15 30 45 60 75 90 105 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset ( v ) i reset ( u a) 628 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-568. atmega6450a: reset pull-up resistor current vs. reset pin voltage (v cc = 2.7v) figure 29-569. atmega6450a: reset pull-up resistor current vs. reset pin voltage (v cc = 1.8v) 8 5 c 25 c -45 c 0 6 12 1 8 24 30 36 42 4 8 54 60 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 2.7 v reset ( v ) i reset ( u a) 8 5 c 25 c -45 c 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v reset ( v ) i reset ( u a) 629 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.10.8 pin driver strength figure 29-570. atmega6450a: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =5v) figure 29-571. atmega6450a: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =2.7v) 8 5 c 25 c -45 c 4.55 4.6 4.65 4.7 4.75 4. 8 4. 8 5 4.9 4.95 5 01234567 8 910 i oh (ma) v oh ( v ) 8 5 c 25 c -45 c 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 01234567 8 910 i oh (ma) v oh ( v ) 630 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-572. atmega6450a: i/o pin output voltage vs. source current, ports a, c, d, e, f, g (v cc =1.8v) figure 29-573. atmega6450a: i/o pin output voltage vs. source current, port b (v cc = 5v) 8 5 c 25 c -45 c 1.2 1.3 1.4 1.5 1.6 1.7 1. 8 0 0.5 1 1.5 2 2.5 3 3.5 4 i oh (ma) v oh ( v ) 8 5 c 25 c -45 c 4.3 4.4 4.5 4.6 4.7 4. 8 4.9 5 0246 8 10 12 14 16 1 8 20 i oh (ma) v oh ( v ) 631 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-574. atmega6450a: i/o pin output voltage vs. source current, port b (v cc = 2.7v) figure 29-575. atmega6450a: i/o pin output voltage vs. source current, port b (v cc = 1.8v) 8 5 c 25 c -45 c 1.2 1.4 1.6 1. 8 2 2.2 2.4 2.6 2. 8 0246 8 10 12 14 16 1 8 20 i oh (ma) v oh ( v ) 8 5 c 25 c -45 c 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1. 8 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i oh (ma) v oh ( v ) 632 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-576. atmega6450a: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 5v) figure 29-577. atmega6450a: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 2.7v) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol ( v ) 8 5 c 25 c -45 c 0 0.2 0.4 0.6 0. 8 1 1.2 01234567 8 910 i ol (ma) v ol ( v ) 633 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-578. atmega6450a: i/o pin output voltage vs. sink current, ports a, c, d, e, f, g (v cc = 1.8v) figure 29-579. atmega6450a: i/o pin output voltage vs. sink current, port b (v cc = 5v) 8 5 c 25 c -45 c 0 0.04 0.0 8 0.12 0.16 0.2 0.24 0.2 8 0.32 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 i ol (ma) v ol ( v ) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol ( v ) 634 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-580. atmega6450p: i/o pin output voltage vs. sink current, port b (v cc = 2.7v) figure 29-581. atmega6450p: i/o pin output voltage vs. sink current, port b (v cc = 1.8v) 8 5 c 25 c -45 c 0 0.2 0.4 0.6 0. 8 1 1.2 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol ( v ) 8 5 c 25 c -45 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 i ol (ma) v ol ( v ) 635 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.10.9 pin threshold and hysteresis figure 29-582. atmega6450p: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 29-583. atmega6450p: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0? 8 5 c 25 c -45 c 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -45 c 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 636 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-584. atmega6450p: i/o pin input hysteresis vs. v cc figure 29-585. atmega6450p: reset input threshold voltage vs. v cc ( v ih ,reset pin read as ?1? ) 8 5 c 25 c -45 c 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis ( v ) -45 c 8 5 c 25 c -45 c 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 637 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-586. atmega6450p: reset input threshold voltage vs. v cc (v il ,reset pin read as ?0?) figure 29-587. atmega6450p: reset input pin hysteresis vs. v cc 8 5 c 25 c -45 c 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -45 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis (m v ) 638 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 29.10.10 bod thresholds and analog comparator offset figure 29-588. atmega6450p: bod thresholds vs. temperature (bod level is 4.3v) figure 29-589. atmega6450p: bod thresholds vs. temperature (bod level is 2.7v) rising v cc falling v cc 4.29 4.31 4.33 4.35 4.37 4.39 4.41 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) rising v cc falling v cc 2.6 8 5 2.695 2.705 2.715 2.725 2.735 2.745 2.755 2.765 2.775 2.7 8 5 2.795 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) 639 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-590. atmega6450p: bod thresholds vs. temperature (bod level is 1.8v) figure 29-591. atmega6450p: bandgap voltage vs. v cc rising v cc falling v cc 1. 8 1. 8 05 1. 8 1 1. 8 15 1. 8 2 1. 8 25 1. 8 3 1. 8 35 1. 8 4 1. 8 45 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bod threshold ( v ) 8 5 c 25 c -45 c 1.0 8 3 1.0 8 5 1.0 8 7 1.0 8 9 1.091 1.093 1.095 1.097 1.099 1.101 1.103 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) bandgap v oltage ( v ) 640 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-592. atmega6450p: bandgap voltage vs. temperature 29.10.11 internal oscillator speed figure 29-593. atmega6450p: w atchdog oscillator frequency vs. v cc 1.092 1.094 1.096 1.09 8 1.1 1.102 1.104 1.106 1.10 8 1.11 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) bandgap v oltage ( v ) 1. 8 v 5.5 v 5.0 v 3.3 v 8 5 c 25 c -45 c 1050 10 8 0 1110 1140 1170 1200 1230 1260 1290 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) f rc (khz) 641 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-594. atmega6450p: w atchdog oscillator freq uency vs. temperature figure 29-595. atmega6450p: calibrated 8mhz rc os cillator frequency vs. temperature 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 1050 10 8 0 1110 1140 1170 1200 1230 1260 1290 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) f rc (khz) 5.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 7.3 7.4 7.5 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 8 5 temperat u re (c) f rc (mhz) 642 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-596. atmega6450p: calibrated 8mhz rc oscillator frequency vs. v cc figure 29-597. atmega6450p: calibrated 8mhz rc osc illator frequency vs. osccal value 8 5 c 25 c -45 c 7.3 7.4 7.5 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) f rc (mhz) 8 5 c 25 c -45 c 2 4 6 8 10 12 14 16 1 8 016324 8 64 8 09611212 8 144 160 176 192 20 8 224 240 256 osccal (x1) f rc (mhz) 643 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.10.12 current consumption of peripheral units figure 29-598. atmega6450p: brownout detector current vs. v cc figure 29-599. atmega6450p: active supply current with adc at 50khz vs. v cc 8 5 c 25 c -45 c 12 15 1 8 21 24 27 30 33 36 39 42 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 120 150 1 8 0 210 240 270 300 330 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 644 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-600. atmega6450p: active supply current with adc at 200khz vs. v cc figure 29-601. atmega6450p: active supply current with adc at 1mhz vs. v cc 8 5 c 25 c -45 c 120 150 1 8 0 210 240 270 300 330 360 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 130 160 190 220 250 2 8 0 310 340 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 645 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 figure 29-602. atmega6450p: aref external reference current vs. v cc figure 29-603. atmega6450p: w atchdog timer current vs. v cc 8 5 c 25 c -45 c 50 65 8 0 95 110 125 140 155 170 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 2 4 6 8 10 12 14 16 1 8 1.522.533.544.555.5 v cc ( v ) i cc ( u a) 646 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-604. atmega6450p: analog comparator current vs. v cc figure 29-605. atmega6450p: programming current vs. v cc 8 5 c 25 c -45 c 30 40 50 60 70 8 0 90 100 110 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -45 c 2 4 6 8 10 12 14 16 1 8 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 647 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.10.13 current consumption in reset and reset pulswidth figure 29-606. atmega6450p: reset supply current vs. v cc (0.1 - 1.0mhz, excluding current through the reset pull-up) figure 29-607. atmega6450p: reset supply current vs. v cc (1 - 16mhz, excluding current through the reset pull-up) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 0.3 0.6 0.9 1.2 1.5 1. 8 2.1 2.4 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 648 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 figure 29-608. atmega6450p: minimum reset pulse w idth vs. v cc 8 5 c 25 c -45 c 0 300 600 900 1200 1500 1 8 00 2100 2400 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) p u lse w idth (ns) 649 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 30. register summary note: registers with bold type only available in atmega3250a/3250pa/6450a/6450p. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved (0xfe) reserved (0xfd) reserved (0xfc) reserved (0xfb) reserved (0xfa) reserved (0xf9) reserved (0xf8) reserved (0xf7) reserved (0xf6) reserved (0xf5) reserved (0xf4) reserved (0xf3) reserved (0xf2) reserved (0xf1) reserved (0xf0) reserved (0xef) reserved (0xee) reserved (0xed) reserved (0xec) reserved (0xeb) reserved - - - - - - - - (0xea) reserved - - - - - - - - (0xe9) reserved - - - - - - - - (0xe8) reserved - - - - - - - - (0xe7) reserved (0xe6) reserved (0xe5) reserved (0xe4) reserved (0xe3) reserved - - - - - - - - (0xe2) reserved - - - - - - - - (0xe1) reserved - - - - - - - - (0xe0) reserved - - - - - - - - (0xdf) reserved - - - - - - - - (0xde) reserved - - - - - - - - (0xdd) portj - portj6 portj5 portj4 portj3 portj2 portj1 portj0 93 (0xdc) ddrj - ddj6 ddj5 ddj4 ddj3 ddj2 ddj1 ddj0 93 (0xdb) pinj - pinj6 pinj5 pinj4 pinj3 pinj2 pinj1 pinj0 93 (0xda) porth porth7 porth6 porth5 porth4 porth3 porth2 porth1 porth0 92 (0xd9) ddrh ddh7 ddh6 ddh5 ddh4 ddh3 ddh2 ddh1 ddh0 93 (0xd8) pinh pinh7 pinh6 pinh5 pinh 4 pinh3 pinh2 pinh1 pinh0 93 (0xd7) reserved - - - - - - - - (0xd6) reserved - - - - - - - - (0xd5) reserved - - - - - - - - (0xd4) reserved - - - - - - - - (0xd3) reserved - - - - - - - - (0xd2) reserved - - - - - - - - (0xd1) reserved - - - - - - - - (0xd0) reserved - - - - - - - - (0xcf) reserved - - - - - - - - (0xce) reserved - - - - - - - - (0xcd) reserved - - - - - - - - (0xcc) reserved - - - - - - - - (0xcb) reserved - - - - - - - - (0xca) reserved - - - - - - - - (0xc9) reserved - - - - - - - - (0xc8) reserved - - - - - - - - (0xc7) reserved - - - - - - - - (0xc6) udr0 usart0 data register 193 (0xc5) ubrr0h usart0 baud rate register high 197 650 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 (0xc4) ubrr0l usart0 baud rate register low 197 (0xc3) reserved - - - - - - - - (0xc2) ucsr0c - umsel0 upm01 upm00 usbs0 ucsz01 ucsz00 ucpol0 195 (0xc1) ucsr0b rxcie0 txcie0 udrie0 rxen 0 txen0 ucsz02 rxb80 txb80 194 (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 193 (0xbf) reserved - - - - - - - - (0xbe) reserved - - - - - - - - (0xbd) reserved - - - - - - - - (0xbc) reserved - - - - - - - - (0xbb) reserved - - - - - - - - (0xba) usidr usi data register 206 (0xb9) usisr usisif usioif usipf usidc us icnt3 usicnt2 usicnt1 usicnt0 206 (0xb8) usicr usisie usioie usi w m1 usi w m0 usics1 usics0 usiclk usitc 207 (0xb7) reserved - - - - - - - - (0xb6) assr - - - exclk as2 tcn2ub ocr2ub tcr2ub 157 (0xb5) reserved - - - - - - - - (0xb4) reserved - - - - - - - - (0xb3) ocr2a timer/counter 2 output compare register a 156 (0xb2) tcnt2 timer/counter2 156 (0xb1) reserved - - - - - - - - (0xb0) tccr2a foc2a w gm20 com2a1 com2a0 w gm21 cs22 cs21 cs20 154 (0xaf) reserved - - - - - - - - (0xae) reserved - - - - - - - - (0xad) reserved - - - - - - - - (0xac) reserved - - - - - - - - (0xab) reserved - - - - - - - - (0xaa) reserved - - - - - - - - (0xa9) reserved - - - - - - - - (0xa8) reserved - - - - - - - - (0xa7) reserved - - - - - - - - (0xa6) reserved - - - - - - - - (0xa5) reserved - - - - - - - - (0xa4) reserved - - - - - - - - (0xa3) reserved - - - - - - - - (0xa2) reserved - - - - - - - - (0xa1) reserved - - - - - - - - (0xa0) reserved - - - - - - - - (0x9f) reserved - - - - - - - - (0x9e) reserved - - - - - - - - (0x9d) reserved - - - - - - - - (0x9c) reserved - - - - - - - - (0x9b) reserved - - - - - - - - (0x9a) reserved - - - - - - - - (0x99) reserved - - - - - - - - (0x98) reserved - - - - - - - - (0x97) reserved - - - - - - - - (0x96) reserved - - - - - - - - (0x95) reserved - - - - - - - - (0x94) reserved - - - - - - - - (0x93) reserved - - - - - - - - (0x92) reserved - - - - - - - - (0x91) reserved - - - - - - - - (0x90) reserved - - - - - - - - (0x8f) reserved - - - - - - - - (0x8e) reserved - - - - - - - - (0x8d) reserved - - - - - - - - (0x8c) reserved - - - - - - - - (0x8b) ocr1bh timer/counter1 output compare register b high 134 (0x8a) ocr1bl timer/counter1 output compare register b low 134 (0x89) ocr1ah timer/counter1 output compare register a high 134 (0x88) ocr1al timer/counter1 output compare register a low 134 (0x87) icr1h timer/counter1 input capture register high 135 (0x86) icr1l timer/counter1 input capture register low 135 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 651 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 (0x85) tcnt1h timer/counter1 high 134 (0x84) tcnt1l timer/counter1 low 134 (0x83) reserved ? ? ? ? ? ? ? ? (0x82) tccr1c foc1a foc1b ? ? ? ? ? ?133 (0x81) tccr1b icnc1 ices1 ? w gm13 w gm12 cs12 cs11 cs10 132 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 ? ? w gm11 w gm10 130 (0x7f) didr1 ? ? ? ? ? ? ain1d ain0d 213 (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d 231 (0x7d) reserved ? ? ? ? ? ? ? ? (0x7c) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 227 (0x7b) adcsrb ?acme ? ? ? adts2 adts1 adts0 231 (0x7a) adcsra aden adsc adate adi f adie adps2 adps1 adps0 229 (0x79) adch adc data register high 230 (0x78) adcl adc data register low 230 (0x77) reserved ? ? ? ? ? ? ? ? (0x76) reserved ? ? ? ? ? ? ? ? (0x75) reserved ? ? ? ? ? ? ? ? (0x74) reserved ? ? ? ? ? ? ? ? (0x73) pcmsk3 ? pcint30 pcint29 pcint28 pcint27 pcint26 pcint25 pcint24 66 (0x72) reserved ? ? ? ? ? ? ? ? (0x71) reserved ? ? ? ? ? ? ? ? (0x70) timsk2 ? ? ? ? ? ? ocie2a toie2 157 (0x6f) timsk1 ? -icie1 ? ? ocie1b ocie1a toie1 135 (0x6e) timsk0 ? ? ? ? ? ? ocie0a toie0 107 (0x6d) pcmsk2 pcint23 pcint22 pcint21 pcint20 pcint19 pcint18 pcint17 pcint16 67 (0x6c) pcmsk1 pcint15 pcint14 pcint13 pcint 12 pcint11 pcint10 pcint9 pcint8 66 (0x6b) pcmsk0 pcint7 pcint6 pcint5 pcin t4 pcint3 pcint2 pcint1 pcint0 67 (0x6a) reserved ? ? ? ? ? ? ? ? (0x69) eicra ? ? ? ? ? ?isc01isc0064 (0x68) reserved ? ? ? ? ? ? ? ? (0x67) reserved ? ? ? ? ? ? ? ? (0x66) osccal oscillator calibration register [cal7:0] 37 (0x65) reserved ? ? ? ? ? ? ? ? (0x64) prr ? ? ? ? prtim1 prspi psusart0 pradc 45 (0x63) reserved ? ? ? ? ? ? ? ? (0x62) reserved ? ? ? ? ? ? ? ? (0x61) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 37 (0x60) w dtcr ? ? ? w dce w de w dp2 w dp1 w dp0 53 0x3f (0x5f) sreg i t h s v n z c 12 0x3e (0x5e) sph stack pointer high 15 0x3d (0x5d) spl stack pointer low 15 0x3c (0x5c) reserved ? ? ? ? ? ? ? ? 0x3b (0x5b) reserved ? ? ? ? ? ? ? ? 0x3a (0x5a) reserved ? ? ? ? ? ? ? ? 0x39 (0x59) reserved ? ? ? ? ? ? ? ? 0x38 (0x58) reserved ? ? ? ? ? ? ? ? 0x37 (0x57) spmcsr spmie r ww sb ?r ww sre blbset pg w rt pgers spmen 281 0x36 (0x56) reserved ? ? ? ? ? ? ? ? 0x35 (0x55) mcucr jtd bods bodse pud ? ? ivsel ivce 61/90/265 0x34 (0x54) mcusr ? ? ?jtrf w drf borf extrf porf 53 0x33 (0x53) smcr ? ? ? ? sm2 sm1 sm0 se 53 0x32 (0x52) reserved ? ? ? ? ? ? ? ? 0x31 (0x51) ocdr idrd/ocdr7 ocdr6 ocdr5 o cdr4 ocdr3 ocdr2 ocdr1 ocdr0 238 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 212 0x2f (0x4f) reserved ? ? ? ? ? ? ? ? 0x2e (0x4e) spdr spi data register 168 0x2d (0x4d) spsr spif w col ? ? ? ? ? spi2x 167 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 166 0x2b (0x4b) gpior2 general purpose i/o register 27 0x2a (0x4a) gpior1 general purpose i/o register 27 0x29 (0x49) reserved ? ? ? ? ? ? ? ? 0x28 (0x48) reserved ? ? ? ? ? ? ? ? 0x27 (0x47) ocr0a timer/counter0 output compare a 107 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 652 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 note: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specif ied bit, and can therefore be used on regi sters containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 4. w hen using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. w hen addressing i/o registers as data space using ld and st instruct ions, 0x20 must be added to these addresses. the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6 450p is a complex microcontroller with more periph- eral units than can be supported within the 64 location rese rved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x26 (0x46) tcnt0 timer/counter0 107 0x25 (0x45) reserved ? ? ? ? ? ? ? ? 0x24 (0x44) tccr0a foc0a w gm00 com0a1 com0a0 w gm01 cs02 cs01 cs00 105 0x23 (0x43) gtccr tsm ? ? ? ? ? psr2 psr10 139/158 0x22 (0x42) eearh ? ? ? ? ? eeprom address register high 26 0x21 (0x41) eearl eeprom address register low 26 0x20 (0x40) eedr eeprom data register 26 0x1f (0x3f) eecr ? ? ? ? eerie eem w eee w eeere 27 0x1e (0x3e) gpior0 general purpose i/o register 28 0x1d (0x3d) eimsk pcie pcie2 pcie1 pcie0 ? ? ?int064 0x1c (0x3c) eifr pcif3 pcif2 pcif1 pcif0 ? ? ? intf0 65 0x1b (0x3b) reserved ? ? ? ? ? ? ? ? 0x1a (0x3a) reserved ? ? ? ? ? ? ? ? 0x19 (0x39) reserved ? ? ? ? ? ? ? ? 0x18 (0x38) reserved ? ? ? ? ? ? ? ? 0x17 (0x37) tifr2 ? ? ? ? ? ?ocf2atov2157 0x16 (0x36) tifr1 ? ?icf1 ? ?ocf1bocf1atov1136 0x15 (0x35) tifr0 ? ? ? ? ? ?ocf0atov0139 0x14 (0x34) portg ? ? ? portg4 portg3 portg2 portg1 portg0 92 0x13 (0x33) ddrg ? ? ? ddg4 ddg3 ddg2 ddg1 ddg0 92 0x12 (0x32) ping ? ? ping5 ping4 ping3 ping2 ping1 ping0 92 0x11 (0x31) portf portf7 portf6 portf5 portf4 portf3 portf2 portf1 portf0 92 0x10 (0x30) ddrf ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 92 0x0f (0x2f) pinf pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 92 0x0e (0x2e) porte porte7 porte6 porte5 porte4 porte3 porte2 porte1 porte0 91 0x0d (0x2d) ddre dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 91 0x0c (0x2c) pine pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 92 0x0b (0x2b) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 91 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 91 0x09 (0x29) pind pind7 pind6 pind5 pind4 p ind3 pind2 pind1 pind0 91 0x08 (0x28) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 91 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 91 0x06 (0x26) pinc pinc7 pinc6 pinc5 pinc4 p inc3 pinc2 pinc1 pinc0 91 0x05 (0x25) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 90 0x04 (0x24) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 90 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 90 0x02 (0x22) p o rta p o rta 7 p o rta 6 p o rta 5 p o rta 4 p o rta 3 p o rta 2 p o rta 1 p o rta 0 9 0 0x01 (0x21) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 90 0x00 (0x20) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 90 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 653 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 31. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adi w rdl,k add immediate to w ord rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbi w rdl,k subtract immediate from w ord rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 ? (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 ? (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc knone3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 call k direct subroutine call pc knone4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 654 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 s w ap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 mov w rd, rr copy register w ord rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 mnemonics operands description operation flags #clocks 655 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 w dr w atchdog reset (see specific descr. for w dr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks 656 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 32. ordering information 32.1 atmega165a notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 27-1 on page 324 . 4. tape & reel 5. see appendix a - atmega165a/165pa/ 325p/3250p specification at 105c speed (mhz) (3) power supply ordering code (2) package (1) operation range 16 1.8 - 5.5v atmega165a-au atmega165a-aur (4) atmega165a-mu atmega165a-mur (4) atmega165a-mch atmega165a-mchr (4) 64a 64a 64m1 64m1 64mc 64mc industrial (-4 0 c to 85 c) atmega165a-an atmega165a-anr (4) atmega165a-mn atmega165a-mnr (4) 64a 64a 64m1 64m1 extended (-4 0 c to 105 c) (5) package type 64a 64-lead, thin (1.0mm) plastic gull w ing quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, quad flat no-lead/micro lead frame package (qfn/ mlf) 64mc 64-lead (2-row staggered), 7 x 7 x 1.0 mm body, 4.0 x 4.0mm exposed pad, quad flat no-lead package (qfn) 657 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 32.2 atmega165pa notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 27-1 on page 324 . 4. tape & reel. 5. see appendix a - atmega165a/165pa/ 325p/3250p specification at 105c. speed (mhz) (3) power supply ordering code (2) package (1) operation range 16 1.8 - 5.5v atmega165pa-au atmega165pa-aur (4) atmega165pa-mu atmega165pa-mur (4) atmega165pa-mch ATMEGA165PA-MCHR (4) 64a 64a 64m1 64m1 64mc 64mc industrial (-4 0 c to 85 c) atmega165pa-an atmega165pa-anr (4) atmega165pa-mn atmega165pa-mnr (4) 64a 64a 64m1 64m1 extended (-4 0 c to 105 c) (5) package type 64a 64-lead, thin (1.0mm) plastic gull w ing quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, quad flat no-lead/micro lead frame package (qfn/ mlf) 64mc 64-lead (2-row staggered), 7 x 7 x 1.0mm body, 4.0 x 4. 0 mm exposed pad, quad flat no-lead package (qfn) 658 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 32.3 atmega325a notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 27-1 on page 324 . 4. tape & reel speed (mhz) (3) power supply ordering code (2) package (1) operation range 20 1.8 - 5.5v atmega325a-au atmega325a-aur (4) atmega325a-mu atmega325a-mur (4) 64a 64a 64m1 64m1 industrial (-4 0 c to 85 c) package type 64a 64-lead, thin (1.0mm) plastic gull w ing quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, quad flat no-lead/micro lead frame package (qfn/ mlf) 659 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 32.4 atmega325pa notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 27-1 on page 324 . 4. tape & reel speed (mhz) (3) power supply ordering code (2) package (1) operation range 20 1.5 - 5.5v atmega325pa-au atmega325pa-aur (4) atmega325pa-mu atmega325pa-mur (4) 64a 64a 64m1 64m1 industrial (-4 0 c to 85 c) package type 64a 64-lead, thin (1.0mm) plastic gull w ing quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, quad flat no-lead/micro lead frame package (qfn/ mlf) 660 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 32.5 atmega3250a notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 27-1 on page 324 . 4. tape & reel speed (mhz) (3) power supply ordering code (2) package (1) operation range 20 1.5 - 5.5v atmega3250a-au atmega3250a-aur (4) 100a 100a industrial (-4 0 c to 85 c) package type 100a 100-lead, 14 x 14 x 1.0mm, 0.5m m lead pitch, thin profile pl astic quad flat package (tqfp) 661 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 32.6 atmega3250pa notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 27-1 on page 324 . 4. tape & reel speed (mhz) (3) power supply ordering code (2) package (1) operation range 20 1.5 - 5.5v atmega3250pa-au atmega3250pa-aur (4) 100a 100a industrial (-4 0 c to 85 c) package type 100a 100-lead, 14 x 14 x 1.0mm, 0.5m m lead pitch, thin profile pl astic quad flat package (tqfp) 662 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 32.7 atmega645a notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 27-1 on page 324 . 4. tape & reel speed (mhz) (3) power supply ordering code (2) package (1) operation range 20 1.8 - 5.5v atmega645a-au atmega645a-aur (4) atmega645a-mu atmega645a-mur (4) 64a 64a 64m1 64m1 industrial (-4 0 c to 85 c) package type 64a 64-lead, thin (1.0mm) plastic gull w ing quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, quad flat no-lead/micro lead frame package (qfn/ mlf) 663 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 32.8 atmega645p notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 27-1 on page 324 . 4. tape & reel speed (mhz) (3) power supply ordering code (2) package (1) operation range 20 1.8 - 5.5v atmega645p-au atmega645p-aur (4) atmega645p-mu atmega645p-mur (4) 64a 64a 64m1 64m1 industrial (-4 0 c to 85 c) package type 64a 64-lead, thin (1.0mm) plastic gull w ing quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, quad flat no-lead/micro lead frame package (qfn/ mlf) 664 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 32.9 atmega6450a notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 27-1 on page 324 . 4. tape & reel speed (mhz) (3) power supply ordering code (2) package (1) operation range 20 1.8 - 5.5v atmega6450a-au atmega6450a-aur (4) 100a 100a industrial (-4 0 c to 85 c) package type 100a 100-lead, 14 x 14 x 1.0mm, 0.5m m lead pitch, thin profile pl astic quad flat package (tqfp) 665 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 32.10 atmega6450p notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 27-1 on page 324 . 4. tape & reel speed (mhz) (3) power supply ordering code (2) package (1) operation range 20 1.8 - 5.5v atmega6450p-au atmega6450p-aur (4) 100a 100a industrial (-4 0 c to 85 c) package type 100a 100-lead, 14 x 14 x 1.0mm, 0.5m m lead pitch, thin profile pl astic quad flat package (tqfp) 666 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 33. packaging information 33.1 64a 2325 orch a rd p a rkw a y s a n jo s e, ca 95131 title drawing no. r rev. 64a, 64-le a d, 14 x 14 mm body size, 1.0 mm body thickne ss , 0.8 mm le a d pitch, thin profile pl as tic q ua d fl a t p a ck a ge (tqfp) c 64a 2010-10-20 pin 1 identifier 0~7 pin 1 l c a1 a2 a d1 d e e1 e b common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note note s : 1.thi s p a ck a ge conform s to jedec reference ms-026, v a ri a tion aeb. 2. dimen s ion s d1 a nd e1 do not incl u de mold protr us ion. allow ab le protr us ion i s 0.25 mm per s ide. dimen s ion s d1 a nd e1 a re m a xim u m pl as tic b ody s ize dimen s ion s incl u ding mold mi s m a tch. 3. le a d copl a n a rity i s 0.10 mm m a xim u m. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 note 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ 2325 orch a rd p a rkw a y s a n jo s e, ca 95131 title drawing no. r rev. 64a, 64-le a d, 14 x 14 mm body size, 1.0 mm body thickne ss , 0.8 mm le a d pitch, thin profile pl as tic q ua d fl a t p a ck a ge (tqfp) c 64a 2010-10-20 pin 1 identifier 0~7 pin 1 l c a1 a2 a d1 d e e1 e b common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note note s : 1.thi s p a ck a ge conform s to jedec reference ms-026, v a ri a tion aeb. 2. dimen s ion s d1 a nd e1 do not incl u de mold protr us ion. allow ab le protr us ion i s 0.25 mm per s ide. dimen s ion s d1 a nd e1 a re m a xim u m pl as tic b ody s ize dimen s ion s incl u ding mold mi s m a tch. 3. le a d copl a n a rity i s 0.10 mm m a xim u m. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 note 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ 667 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 33.2 64m1 2325 orch a rd p a rkw a y s a n jo s e, ca 95131 title drawing no. r rev. 64m1 , 64-p a d, 9 x 9 x 1.0 mm body, le a d pitch 0.50 mm, h 64m1 2010-10-19 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 b 0.18 0.25 0.30 d d2 5.20 5.40 5.60 8.90 9.00 9.10 8.90 9.00 9.10 e e2 5.20 5.40 5.60 e 0.50 bsc l 0.35 0.40 0.45 note s : 1. jedec st a nd a rd mo-220, (saw sing u l a tion) fig. 1, vmmd. 2. dimen s ion a nd toler a nce conform to asmey14.5m-1994. top view s ide view bottom view d e m a rked pin# 1 id seating plane a1 c a c 0.08 1 2 3 k 1.25 1.40 1.55 e2 d2 b e pin #1 corner l pin #1 tr i a ngle pin #1 ch a mfer (c 0.30) option a option b pin #1 notch (0.20 r) option c k k 5.40 mm expo s ed p a d, micro le a d fr a me p a ck a ge (mlf) 2325 orch a rd p a rkw a y s a n jo s e, ca 95131 title drawing no. r rev. 64m1 , 64-p a d, 9 x 9 x 1.0 mm body, le a d pitch 0.50 mm, h 64m1 2010-10-19 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 b 0.18 0.25 0.30 d d2 5.20 5.40 5.60 8.90 9.00 9.10 8.90 9.00 9.10 e e2 5.20 5.40 5.60 e 0.50 bsc l 0.35 0.40 0.45 note s : 1. jedec st a nd a rd mo-220, (saw sing u l a tion) fig. 1, vmmd. 2. dimen s ion a nd toler a nce conform to asmey14.5m-1994. top view s ide view bottom view d e m a rked pin# 1 id seating plane a1 c a c 0.08 1 2 3 k 1.25 1.40 1.55 e2 d2 b e pin #1 corner l pin #1 tr i a ngle pin #1 ch a mfer (c 0.30) option a option b pin #1 notch (0.20 r) option c k k 5.40 mm expo s ed p a d, micro le a d fr a me p a ck a ge (mlf) 668 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 33.3 64mc title drawing no. gpc rev. packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com 64mc zxc a 64mc, 64qfn (2-row st a ggered), 7 x 7 x 1.00 mm body, 4.0 x 4.0 mm expo s ed p a d, q ua d fl a t no le a d p a ck a ge 10/3/07 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 0.00 0.02 0.05 b 0.18 0.23 0.28 c 0.20 ref d 6.90 7.00 7.10 d2 3.95 4.00 4.05 e 6.90 7.00 7.10 e2 3.95 4.00 4.05 et ? 0.65 ? er ? 0.65 ? k 0.20 ? ? (ref) l 0.35 0.40 0.45 y 0.00 ? 0.075 s ide view top view bottom view note: 1. the termin a l #1 id i s a l as er-m a rked fe a t u re . pin 1 id d e a1 a y c et/2 r0.20 0.40 b1 a1 b30 a34 b a8 b7 et d2 b16 a18 b22 a25 e2 k (0.1) ref b8 a9 (0.18) ref l b15 a17 l er a26 b23 et 669 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 33.4 100a 2325 orch a rd p a rkw a y s a n jo s e, ca 95131 title drawing no. r rev. 100a, 100-le a d, 14 x 14 mm body size, 1.0 mm body thickne ss , 0.5 mm le a d pitch, thin profile pl as tic q ua d fl a t p a ck a ge (tqfp) d 100a 2010-10-20 pin 1 identifier 0~7 pin 1 l c a1 a2 a d1 d e e1 e b a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 note 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 note 2 b 0.17 ? 0.27 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.50 typ note s : 1. thi s p a ck a ge conform s to jedec reference ms-026, v a ri a tion aed. 2. dimen s ion s d1 a nd e1 do not incl u de mold protr us ion. allow ab le protr us ion i s 0.25 mm per s ide. dimen s ion s d1 a nd e1 a re m a xim u m pl as tic b ody s ize dimen s ion s incl u ding mold mi s m a tch. 3. le a d copl a n a rity i s 0.08 mm m a xim u m. common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note 670 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 34. errata 34.1 atmega165a/165pa/325a/ 325pa/3250a/3250pa/645a/645 p/6450a/6450p rev. g no known errata. 34.2 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/6 450a/6450p rev. a to f not sampled. 671 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 35. datasheet revision history please note that the referring page numbers in this section are referring to this document. the referring revisions in this section are referring to the document revision. 35.1 8285b ? 03/11 35.2 8285a ? 09/10 1. updated the datasheet according to the atmel new brand style guide 2. updated ?signature bytes? , table 26.3 on page 286 . 3. updated the power supply voltage (1.5 - 5.5v) for all devices in . ?ordering information? on page 656 . 4. added ?ordering information? for extended temperature (-40c to 105c) 1. initial revision (based on the atmega165p/325p/32 50p/645/6450/v). 2. changes done compared to atmega165 p/325p/3250p/645/6450/v datasheet: ? new eimsk and eifr register overview ? new graphics in ?typical characteristics? on page 332 . ? ordering information includes tape & reel ?new ?ordering information? on page 656 . ? qtouch library support features 672 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 i 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 pin configurations ..... ................ ................. ................ ................. ............ 2 1.1pinout - tqfp and qfn/mlf ....................................................................................2 1.2pinout - 100a (tqfp) ................................................................................................3 2 overview ............ ................ ................ ............... .............. .............. ............ 4 2.1block diagram ...........................................................................................................4 2.2comparison between atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p 6 2.3pin descriptions ........................................................................................................6 3 resources .............. .............. .............. ............... .............. .............. ............ 9 4 data retention .......... ................ ................ ................. ................ ............... 9 5 about code examples ........ .............. ............... .............. .............. ............ 9 6 avr cpu core ................. ................ ................. .............. .............. .......... 10 6.1introduction ..............................................................................................................1 0 6.2architectural overview ............................................................................................10 6.3alu ? arithmetic logic unit ....................................................................................11 6.4avr status register ...............................................................................................11 6.5general purpose register file ................................................................................13 6.6stack pointer ...........................................................................................................14 6.7instruction execution timing ...................................................................................15 6.8reset and interrupt handling ..................................................................................16 7 avr memories .......... ................ ................ ................. ................ ............. 18 7.1in-system reprogrammable flash program memory .............................................18 7.2sram data memory ...............................................................................................19 7.3eeprom data memory ...... ................ ................ ................. ............ ............. ..........21 7.4i/o memory ..............................................................................................................25 7.5general purpose i/o registers ...............................................................................25 7.6register description ................................................................................................26 8 system clock and clock options ................ ................. .............. .......... 29 8.1clock systems and their distribution .......................................................................29 8.2clock sources .........................................................................................................30 8.3default clock source ...............................................................................................31 ii 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 8.4calibrated internal rc oscillator .............................................................................31 8.5crystal oscillator .....................................................................................................32 8.6low-frequency crystal oscillator .............................................................................33 8.7external clock .........................................................................................................35 8.8timer/counter oscillator .........................................................................................36 8.9clock output buffer .................................................................................................36 8.10system clock prescaler ........................................................................................36 8.11register description ..............................................................................................37 9 power management and sleep mo des ............... .............. ............ ........ 39 9.1overview .................................................................................................................39 9.2sleep modes ...........................................................................................................39 9.3bod disable (1) .........................................................................................................39 9.4idle mode .................................................................................................................4 0 9.5adc noise reduction mode ...................................................................................40 9.6power-down mode ..................................................................................................40 9.7power-save mode ...................................................................................................41 9.8standby mode .........................................................................................................41 9.9power reduction register .......................................................................................41 9.10minimizing power consumption ............................................................................41 9.11register description ..............................................................................................44 10 system control and reset .... .............. .............. .............. .............. ........ 46 10.1resetting the avr .................................................................................................46 10.2reset sources .......................................................................................................46 10.3internal voltage reference ....................................................................................50 10.4 w atchdog timer ....................................................................................................50 10.5register description ..............................................................................................53 11 interrupts ............... .............. .............. ............... .............. .............. .......... 55 11.1interrupt vectors ....................................................................................................55 11.2moving interrupts between application and boot space ......................................60 11.3register description ..............................................................................................61 12 external interrupts .......... ................ ................. .............. .............. .......... 62 12.1pin change interrupt timing .................................................................................62 12.2register description ..............................................................................................64 13 i/o-ports ........ ................ ................. ................ ................. .............. .......... 68 iii 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 13.1overview ...............................................................................................................68 13.2ports as general digital i/o ...................................................................................69 13.3alternate port functions ........................................................................................74 13.4register description ..............................................................................................90 14 8-bit timer/counter0 with pw m .............. ................. ................ ............. 94 14.1features ................................................................................................................94 14.2overview ...............................................................................................................94 14.3timer/counter clock sources ...............................................................................95 14.4counter unit ..........................................................................................................95 14.5output compare unit ............................................................................................96 14.6compare match output unit ..................................................................................98 14.7modes of operation ...............................................................................................99 14.8timer/counter timing diagrams .........................................................................103 14.9register description ............................................................................................105 15 16-bit timer/counter1 ......... .............. ............... .............. .............. ........ 109 15.1features ..............................................................................................................109 15.2overview .............................................................................................................109 15.3accessing 16-bit registers ..................................................................................111 15.4timer/counter clock sources .............................................................................114 15.5counter unit ........................................................................................................115 15.6input capture unit ...............................................................................................116 15.7output compare units .........................................................................................118 15.8compare match output unit ................................................................................119 15.9modes of operation .............................................................................................121 15.10timer/counter timing diagrams .......................................................................128 15.11register description ..........................................................................................130 16 timer/counter0 and time r/counter1 prescalers ..... .............. ........... 137 16.1prescaler reset ...................................................................................................137 16.2internal clock source ..........................................................................................137 16.3external clock source .........................................................................................137 16.4register description ............................................................................................139 17 8-bit timer/counter2 with pw m and asynchronous operation ...... 140 17.1features ..............................................................................................................140 17.2overview .............................................................................................................140 17.3timer/counter clock sources .............................................................................141 iv 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 17.4counter unit ........................................................................................................141 17.5output compare unit ..........................................................................................142 17.6compare match output unit ................................................................................144 17.7modes of operation .............................................................................................145 17.8timer/counter timing diagrams .........................................................................149 17.9asynchronous operation of the timer/counter ....................................................151 17.10timer/counter prescaler ...................................................................................153 17.11register description ..........................................................................................154 18 spi ? serial peripheral interface ......... .............. .............. ............ ........ 159 18.1features ..............................................................................................................159 18.2overview .............................................................................................................159 18.3ss pin functionality ............................................................................................164 18.4data modes .........................................................................................................165 18.5register description ............................................................................................166 19 usart ............. ................. ................ .............. .............. .............. ........... 169 19.1features ..............................................................................................................169 19.2overview .............................................................................................................169 19.3clock generation .................................................................................................171 19.4frame formats ....................................................................................................174 19.5usart initialization ............................................................................................175 19.6data transmission ? the usart transmitter ....................................................177 19.7data reception ? the usart receiver .............................................................180 19.8asynchronous data reception ............................................................................185 19.9multi-processor communication mode ................................................................188 19.10examples of baud rate setting ........................................................................189 19.11register description ..........................................................................................193 20 usi ? universal seri al interface ............ ................. ................ ............. 198 20.1features ..............................................................................................................198 20.2overview .............................................................................................................198 20.3functional descriptions .......................................................................................199 20.4alternative usi usage .........................................................................................205 20.5register descriptions ..........................................................................................206 21 ac - analog comparator .... .............. ............... .............. .............. ........ 210 21.1analog comparator multiplexed input .................................................................211 21.2register description ............................................................................................212 v 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 22 adc - analog to digital converter ......... ................. ................ ........... 214 22.1features ..............................................................................................................214 22.2overview .............................................................................................................214 22.3operation .............................................................................................................215 22.4starting a conversion ..........................................................................................216 22.5prescaling and conversion timing ......................................................................217 22.6changing channel or reference selection .........................................................219 22.7adc noise canceler ...........................................................................................220 22.8adc conversion result ......................................................................................225 22.9register description ............................................................................................227 23 jtag interface and on-chi p debug system ............ .............. ........... 232 23.1features ..............................................................................................................232 23.2overview .............................................................................................................232 23.3tap ? test access port ......................................................................................233 23.4tap controller .....................................................................................................235 23.5using the boundary-scan chain ..........................................................................236 23.6using the on-chip debug system .......................................................................236 23.7on-chip debug specific jtag instructions .........................................................237 23.8using the jtag programm ing capabilities .........................................................237 23.9on-chip debug related register in i/o memory .................................................238 23.10bibliography .......................................................................................................238 24 ieee 1149.1 (jtag) boundary-scan ....... ................. ................ ........... 239 24.1features ..............................................................................................................239 24.2system overview ................................................................................................239 24.3data registers .....................................................................................................240 24.4boundary-scan specific jtag instructions .........................................................241 24.5boundary-scan chain ..........................................................................................242 24.6boundary-scan order ..........................................................................................251 24.7boundary-scan description language files ........................................................264 24.8boundary-scan related register in i/o memory .................................................265 25 boot loader support ? read-while-wri te self-programming ......... 266 25.1features ..............................................................................................................266 25.2overview .............................................................................................................266 25.3application and boot loader flash sections .......................................................266 25.4read- w hile- w rite and no read- w hile- w rite flash sections ..............................267 vi 8285b?avr?03/11 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/64 5 25.5boot loader lock bits .........................................................................................270 25.6entering the boot loader program ......................................................................271 25.7addressing the flash during self-programming .................................................272 25.8self-programming the flash ................................................................................273 25.9register description ............................................................................................281 26 memory programming ........ .............. ............... .............. .............. ........ 283 26.1program and data memory lock bits .................................................................283 26.2fuse bits .............................................................................................................284 26.3signature bytes ...................................................................................................286 26.4calibration byte ...................................................................................................286 26.5page size ............................................................................................................286 26.6parallel programming parameters, pin mapping, and commands .....................286 26.7parallel programming ..........................................................................................289 26.8serial downloading .............................................................................................298 26.9programming via the jtag interface ..................................................................304 27 electrical characteristics ... .............. ............... .............. .............. ........ 317 27.1absolute maximum ratings* ...............................................................................317 27.2dc characteristics ..............................................................................................317 27.3speed grades .....................................................................................................324 27.4clock characteristics ...........................................................................................325 27.5system and reset characteristics ......................................................................326 27.6power-on reset ...................................................................................................326 27.7brown-out detection ............................................................................................327 27.8external interrupts characteristics ......................................................................327 27.9spi timing characteristics ..................................................................................328 28 adc characteristics ........ .............. .............. .............. .............. ........... 330 29 typical characteristics ....... .............. ............... .............. .............. ........ 332 29.1atmega165a ......................................................................................................332 29.2atmega165pa ....................................................................................................365 29.3atmega325a ......................................................................................................397 29.4atmega325pa ....................................................................................................428 29.5atmega3250a ....................................................................................................459 29.6atmega3250pa ..................................................................................................490 29.7atmega645a ......................................................................................................521 29.8atmega645p ......................................................................................................553 vii 8285b?avr?03/11 atmega165a/165pa/325a/ 325pa/3250a/3250pa/6 29.9atmega6490a ....................................................................................................585 29.10atmega6450p ..................................................................................................617 30 register summary ............ .............. .............. .............. .............. ........... 649 31 instruction set summary ... .............. ............... .............. .............. ........ 653 32 ordering information .......... .............. ............... .............. .............. ........ 656 32.1atmega165a ......................................................................................................656 32.2atmega165pa ....................................................................................................657 32.3atmega325a ......................................................................................................658 32.4atmega325pa ....................................................................................................659 32.5atmega3250a ....................................................................................................660 32.6atmega3250pa ..................................................................................................661 32.7atmega645a ......................................................................................................662 32.8atmega645p ......................................................................................................663 32.9atmega6450a ....................................................................................................664 32.10atmega6450p ..................................................................................................665 33 packaging information .......... ................ ................. ................ ............. 666 33.164a ......................................................................................................................6 66 33.264m1 ...................................................................................................................667 33.364mc ...................................................................................................................668 33.4100a ....................................................................................................................66 9 34 errata ........... ................ ................ ................. ................ .............. ........... 670 34.1atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p rev. g 670 34.2atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p rev. a to f 670 35 datasheet revision history .. ................ ................. ................ ............. 671 35.18285b ? 03/11 .....................................................................................................671 35.28285a ? 09/10 .....................................................................................................671 table of contents.......... ................. ................ ................. ................ ........... i 8285b?avr?03/11 atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel : (+1)(408) 441-0311 fax : (+1)(408) 487-2600 www.atmel.com atmel asia limited unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel : (+852) 2245-6100 fax : (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel : (+49) 89-31970-0 fax : (+49) 89-3194621 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel : (+81)(3) 3523-3551 fax : (+81)(3) 3523-7581 ? 2011 atmel corporation. all rights reserved. / rev. corp0xxxx atmel ? , atmel logo and combinations thereof, avr ? and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection wi th atmel products. no license, ex press or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and conditions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its pro ducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purp ose, or non-infringement. in no even t shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limitati on, damages for loss and prof- its, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or com- pleteness of the contents of th is document and reserves the right to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information cont ained herein. unless specifically provided otherwise, atmel pr oducts are not suit- able for, and shall not be used in, automotive applications. atme l products are not intended, authorized, or warranted for use as components in applica- tions intended to support or sustain life. |
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